K4M28163PH - R(B)E/G/C/F

March 2006

1

Mobile SDRAM

• 1.8V power supply.

• LVCMOS compatible with multiplexed address.

• Four banks operation.

• MRS cycle with address key programs.

-. CAS latency (1, 2 & 3).

-. Burst length (1, 2, 4, 8 & Full page).

-. Burst type (Sequential & Interleave).

• EMRS cycle with address key programs.

• All inputs are sampled at the positive going edge of the system

clock.

• Burst read single-bit write operation.

• Special Function Support.

-. PASR (Partial Array Self Refresh).

-. Internal TCSR (Temperature Compensated Self Refresh)

-. DS (Driver Strength)

-. DPD (Deep Power Down)

• DQM for masking.

• Auto refresh.

• 64ms refresh period (4K cycle).

• Commercial Temperature Operation (-25

°C ~ 70°C).

• Extended Temperature Operation (-25

°C ~ 85°C).

• 54Balls FBGA ( -RXXX -Pb, -BXXX -Pb Free).

FEATURES

The K4M28163PH is 134,217,728 bits synchronous high data

rate Dynamic RAM organized as 4 x 2,098,152 words by 16 bits,

fabricated with SAMSUNG’s high performance CMOS technol-

ogy. Synchronous design allows precise cycle control with the

use of system clock and I/O transactions are possible on every

clock cycle. Range of operating frequencies, programmable

burst lengths and programmable latencies allow the same

device to be useful for a variety of high bandwidth and high per-

formance memory system applications.

GENERAL DESCRIPTION

ORDERING INFORMATION

- R(B)E/G : Normal/Low Power, Extended Temperature(-25

°C ~ 85°C)

- R(B)C/F : Normal/Low Power, Commercial Temperature(-25

°C ~ 70°C)

Notes :

1. In case of 40MHz Frequency, CL1 can be supported.

Part No.

Max Freq.

Interface

Package

K4M28163PH-R(B)E/G/C/F75

133MHz(CL3), 83MHz(CL2)

LVCMOS

54 FBGA Pb

(Pb Free)

K4M28163PH-R(B)E/G/C/F90

111MHz(CL3), 83MHz(CL2)

K4M28163PH-R(B)E/G/C/F1L

2M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA

Address configuration

Organization

Bank

Row

Column Address

8M x 16

BA0, BA1

A0 - A11

A0 - A8

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