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MAS9191A 数据表(PDF) 13 Page - Micro Analog systems |
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MAS9191A 数据表(HTML) 13 Page - Micro Analog systems |
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13 / 36 page ![]() 13 DA9191A.000 July 31, 1997 FUNCTIONS ◆ Data Transmission After a reset the TX block is in power down. The power down mode is controlled by bit TXSIP (TX section in power down) in register 07HEX. The TXRST bit located in register 12 HEX is used every time a TX collision occurs or for any other TX block reset causes. When the device is ready to receive data, the TXWRD bit of register 10HEX is high. If five bytes are written into register 19HEX the data transmission begins. The data is transferred from the serial interface to the TX buffer and the TXWRD bit is set high again, which causes XINT to become active. When the block comes out of power down mode the XINT is active because the device is ready to receive data (TXWRD goes high). The lower nibble of the fifth byte is ignored. The 36 bits of data are coded by the BCH coder with following polynomial: G(x) = x 12 + x10 + x8 + x5 + x4 + x3 + x0 The BCH coder adds 12 parity bits to the data and the data is transferred to the DCC coding block. The DCC coder adds a digital color code on the reverse control channel (RECC) according following table. DCC(1:0) Coded DCC 00 0000000 01 0011111 10 1100011 11 1111100 The framing block adds bit sync (101010...10) and word sync (11100010010) sequences to the frames and performs needed repeats depending on the mode. Reverse control channel data format. The numbers under the frames show the number of bits in each section. Bit sync Word sync Coded DCC First word repeated 5 times Second word repeated 5 times 30 11 7 240 240 Reverse voice channel data format. Bit Sync Word Sync 1.Repeat of word 1 Bit Sync Word Sync 2.Repeat of word 1 Bit Sync Word Sync 101 11 48 37 11 48 37 11 Bit Sync Word Sync 5.Repeat of word 1 Bit Sync Word Sync 1.Repeat of word 2 Bit Sync Word Sync 37 11 48 37 11 48 37 11 Bit Sync Word Sync 5.Repeat of word 2 37 11 48 The Manchester encoder block encodes the data into a Manchester coded format with bit clock. The bit clock is 8kHz in the ETACS mode and 10kHz in the AMPS mode. The mode can be controlled by bit SYS0 of register 12HEX. The data polarity can be inverted with bit INVTX of register 13HEX.If the BUSY bit does not go active between 56 and 104 bits of the transmitted message a transmission collision occurs. In this case the data which is in the TX block and the data that the user is writing to the device will not be transmitted. The TXCOL bit of register 10HEX will go high in this case and cause an interrupt. The TXCOL will remain active until the TX block is reset with the TXRST bit of register 12HEX. If the TXCTREN bit is active in register 12HEX the TXCTRL output turns the transmitter off when a TX collision occurs. If the AUMUT bit in register 13HEX is set to high the TX audio block is muted with switch S19 on the voice channel while data transmission is occurring. |
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