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MAS9191A 数据表(PDF) 16 Page - Micro Analog systems |
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MAS9191A 数据表(HTML) 16 Page - Micro Analog systems |
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16 / 36 page ![]() 16 DA9191A.000 July 31, 1997 FUNCTIONS ◆ SAT detection & regeneration SAT detection is active on voice channel in AMPS or TACS mode (SYS1=0). The supervisory audio tone is detected with a digital PLL. The detector compares the received SAT to the given SAT color code (SCC). When the given SAT is detected the SATDET bit of register 11HEX is set to high. If SATINTEN bit of register 13HEX is on the rising and falling edge of SATDET will cause the interrupt SATINT. On the voice channel the SAT regeneration can be enabled with bit SATEN of register 14HEX. By setting bit NOMSAT of register 14HEX nominal SAT frequency is generated. Otherwise, the SAT output frequency will follow received SAT frequency. The block is in power down mode when the TXSIP (transmit section in power down) bit is active in register 07HEX. After a reset the block is in power down mode. SCC1 SCC0 SAT frequency 0 0 5970 Hz 0 1 6000 Hz 1 0 6030 Hz 1 1 invalid code ◆ SAT, ST or Data Transmission The SAT and signaling tone (ST) are sent only on the voice channel in AMPS or TACS mode (SYS1=0). The SATEN and STON can be used to control the SAT and ST transmission. However, the device will automatically stop transmitting SAT and ST signals whenever data is being transmitted, even though SATEN or STON is high. The signaling tone is 8kHz in ETACS and 10kHz in AMPS. Also, switch S17 for TX data and switch S18 for ST can be used to disable the transmission. The switches must be on during transmission. The control bits for these switches are located in register 0DHEX. The SAT, TXDATA and the ST are summed and amplified with GC8. The gain of the amplifier is -3.75dB...+3.75dB with 16 steps. The adjustment is made with bits 0..3 of register 0DHEX. After being amplified the signal is filtered with 4th order SC filter F12. The cutoff frequency of the filter is 19kHz in AMPS, 15kHz in ETACS and 200Hz in NAMPS (SYS1=1). The gain of the filter at 1kHz is 0dB. In the NAMPS mode, the signal is then fed to low pass filter F15, which is a 2nd order RC type filter. After filtering the signal is summed to the TX audio signal depending on the state of switch S20. The switch is controlled by bit 6 of register 01HEX .Register 07HEX bit AUDIOP is used to set these blocks into power down mode. ◆ DTMF Receiver For enabling answering machine functions, the chip has an internal DTMF receiver. The receiver is in power down mode after a reset. The DTMFRP bit of register 07HEX controls the receiver power down mode. The receiver has two separate filters for separation of the low and high frequencies. The comparator and logic section measures the low and high frequency periods with an averaging algorithm. When the valid DTMF tone is detected the external steering logic output pin EST is set to high. With an external RC time constant the tone detect time and tone dropout times can be adjusted. The STGT input/output pin has an internal comparator and pull- up and pull-down transistors. When EST is active and STGT goes from below to above the Vref level (VDD/2) the STGT is pulled up with an internal transistor. This causes the STD signal to go high, which causes the XINT line to become active. At the same time the detected DTMF tone is stored in register 04HEX. When the DTMF tone is not present the EST will go low, which causes the STGT to fall. When the STGT falls below the Vref level (VDD/2) the internal logic pulls the input down. The external RC circuit will filter out very short gaps in the received DTMF tone. The interrupt caused by the DTMF detector is cleared by reading status register 10HEX. If the interrupt is cleared but register 04HEX is not read until the next DTMF tone is received, then the previous tone will be lost. The formula below can be used to calculate tone present and tone absent times. By adding diodes to the external circuit the tone present and tone dropout times can be altered. If one of the diodes is removed, the absent and present times are calculated using the parallel combination of R1 and R2. EST STGT EST STGT C R2 C R1 R1 Time = R*C ln(VDD/VREF) |
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