7 (8)

DA9178.001

10 Dec, 2003

SAMPLES IN SBDIL 20 PACKAGE

VDD 1

NC 2

QOP 3

NC 4

QI 5

NC 6

QOM 7

NC 8

AGC 9

NC 10

20 VSS

19 NC

18 RFM

17 RFP

16 NC

15 PDN

14 AON

13 DEC

12 NC

11 OUT

Top Marking Definitions:

YYWW = Year Week

XXXXX.X = Lot Number

x =1, 5 Sample Version Number

PIN DESCRIPTION

Pin Name

Pin

Type

Function

Note

VDD

1

P

Positive Power Supply

NC

2

QOP

3

AO

Quartz Filter Output for Crystal

NC

4

1

QI

5

AI

Quartz Filter Input for Crystal and

External Compensation Capacitor

NC

6

1

QOM

7

AO

Quartz Filter Output for External

Compensation Capacitor

NC

8

AGC

9

AO

AGC Capacitor

NC

10

OUT

11

DO

Receiver Output

2

NC

12

DEC

13

AO

Demodulator Capacitor

AON

14

DI

AGC On Control

3

PDN

15

AI

Power Down Input

4

NC

16

RFP

17

AI

Positive Receiver Input

RFM

18

AI

Negative Receiver Input

NC

19

VSS

20

G

Power Supply Ground

Notes:

1) Pins 4 and 6 around quartz crystal filter input pins must be connected to VSS to eliminate DIL package

leadframe parasitic capacitances disturbing the crystal filter performance. All other NC (Not Connected)

pins are also recommended to be connected to VSS to minimize noise coupling.

2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced

(modulated)

-

-

at power down the output is pulled to VSS (pull down switch)

3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)

-

Internal pull-up with current < 1

µA which is switched off at power down

4) PDN = VSS means receiver on; PDN = VDD means receiver off

-

Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up

(PDN=VSS) i.e. at the falling edge of PDN signal.