M95040, M95020, M95010

Connecting to the SPI bus

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Connecting to the SPI bus

These devices are fully compatible with the SPI protocol.

All instructions, addresses and input data bytes are shifted in to the device, most significant

bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)

after Chip Select (S) goes Low.

All output data bytes are shifted out of the device, most significant bit first. The Serial Data

Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction

(such as the Read from Memory Array and Read Status Register instructions) have been

clocked into the device.

Figure 3 shows three devices, connected to an MCU, on a SPI bus. Only one device is

selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the

others being high impedance.

Figure 3.

Bus master and memory devices on the SPI bus

1.

The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

2.

These pull-up resistors, R, ensure that the M950x0 are not selected if the Bus Master leaves the S line in the high-

impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time

(that is when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when

all inputs/outputs become high impedance, S is pulled High while C is pulled Low (thus ensuring that S and C do not

AI12304

Bus Master

SPI Memory

Device

SDO

SDI

SCK

CQD

S

SPI Memory

Device

CQD

S

SPI Memory

Device

CQD

S

CS3

CS2 CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

W

HOLD

W

HOLD

W

HOLD