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MAS9560 数据表(PDF) 22 Page - Micro Analog systems

部件名 MAS9560
功能描述  Stereo Audio Driver DAC
PDF  25 Pages
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制造商  MAS [Micro Analog systems]
网页  http://www.mas-oy.com
标志 MAS - Micro Analog systems

MAS9560 数据表(HTML) 22 Page - Micro Analog systems

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DA9560.001
20 January, 2005
Right AUX Gain Register 0x09
R/W
0
-
0x09[7:5]
-
-
Unused
ARV[4:0] Right AUX pre-amplifier gain
ARV
0x09[4:0]
R/W
00000
00000
00001
...
10101...11111
Mute
-20 dB
in steps of 2 dB
20 dB
AIN Gain Register
0x0A
R/W
0
-
0x0A[7:5]
-
-
Unused
AIV[4:0] AIN pre-amplifier gain
AIV
0x0A[4:0]
R/W
00000
00000
00001
...
10101...11111
Mute
-20 dB
in steps of 2 dB
20 dB
Note: Unused register bit values are undefined.
I2C BUS TIMING
LSVDD = VBAT = 3.6V, EPVDD = HPVDD = VLDO = 2.86V (LDO-mode), -40
°C ≤ TA ≤ +85°C, typical
values at TA = +27°C, unless otherwise noted
Parameter
Pin Name Conditions
Min
Nom
Max
Unit
Input Low Voltage
SCLK,
SDI
tbd
IOVDD
Input High Voltage
SCLK,
SDI
tbd
IOVDD
Start Condition Setup
Time
SCLK,
SDI
tbd
ns
Stop Condition Setup
Time
SCLK,
SDI
tbd
ns
Data Setup Time before
clock rising edge
SCLK,
SDI
tbd
ns
Data Hold Time after
clock falling edge
SCLK,
SDI
tbd
ns
Clock Low Pulse Time
SCLK
tbd
ns
Clock High Pulse Time
SCLK
tbd
ns
Bus Frequency
SCLK
tbd
MHz
Data Output Low Voltage
SCLK,
SDI
ILOAD = 3
mA
tbd
V
Data Output High
Leakage Current
SCLK,
SDI
VSDI = 5 V
tbd
µA
Data Output Hold Time
after clock falling edge
SCLK,
SDI
tbd
ns
Data Output Setup Time
before clock rising edge
SCLK,
SDI
fI2C = 1MHz
tbd
ns



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