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DA9560.001

20 January, 2005

CONTROL INTERFACES

MAS9560 registers (detailed description below) are controlled either via I

written using I

Pin

Bus

Function

MODE

I

Select I

SCLK

I

Serial Data Clock for I

SDI

I

Serial Data I/O for I

SDO

SPI

Serial Data Output for SPI

XCS

SPI

Chip Select for SPI (active low)

DAI

I

Serial Data input for I

WSI

I

Frame Identification for I

CLI

I

Serial Data Clock for I

◆ I

I

bus is a 2-wire serial interface, so two lines, a serial

data line (SDI) and serial clock line (SCLK), are

required. MAS9560 data line is bi-directional for

data acknowledge and transmit, but clock line is

just a receiver, i.e., the clock is gotten from the

master. Default state for both lines is high, since all

devices connected on the bus form together an

AND-function because of pull-up resistors.

A master is controlling the bus, enabling clock and

giving start and stop requests, so data transfer for

MAS9560 is started with start-pulse given by a

master device. As the master is changing SDI level

from high to low while SCLK is high, this action is

recognized as the start pulse. Stop pulse is similarly

created: when SCLK is high SDI level is changed

from low to high. During the data transition data line

(SDI) level may not change when clock (SCLK) is

high, because this is interpreted either as start or

stop pulse.

Data is transmitted in bytes, one byte is 8-bit long.

Several bytes can be sent one by one until the

master gives stop signal.

I

byte in I

device code and transfer mode. Device code is

specified by 7 bits and is 1001 101 for MAS9560,

last (8th) bit selects read/write-mode (r/w): high for

read and low for write. After first byte is read,

MAS9560 acknowledges it by pulling data line (SDI)

down, keeping data line down and releasing the

line only after the master driven clock line (SCLK) is

again pulled down.

After the device specific code MAS9560 is set as

receiver for data as described above, sub-address

is given as a second byte. This addresses the initial

register number, and the following byte is the data

which is written to the register. In case the fourth

byte is written (and no stop bit is given), MAS9560

changes to increment mode and this fourth byte is

written to a following register. All registers can be

written by one start-stop sequence. On-chip

incremental counter is just 4-bits long. Incrementing

stops at address 0x0F to prevent overflow. In write

mode MAS9560 gives acknowledge pulse after

every byte.

I

this case a sequence is as follows: First byte 1001

1010 is written after start pulse (MAS9560

acknowledges) after which register address is

given, which is acknowledged by device. Next a

new start pulse is given by the master and byte

1001 1011 is acknowledged by MAS9560, after

which register (specified in initial sequence) data is

written to data bus (MSB first). After that MAS9560

gives

NAK

(no

acknowledge)

signal

which

continues until ACK (acknowledge) or STOP signal

is given by the master. In case ACK signal is given,

the incremental mode of MAS9560 is enabled and

next register data is written to SDI bus by

MAS9560. The data is again followed by NAK

signal, and the reading sequence can be repeated

or stopped.

Values of unspecified bits in registers with less than

8-bits are not set to any initial value, and their value

can vary from time to time.