Data Sheet

ADL5308

APPLICATIONS INFORMATION

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Rev. 0 | 17 of 22

SDA and SCL Interface

Figure 38 shows the bidirectional SDA interface. The SDA output

driver is open-drain and requires an off-chip pull-up resistor at the

receiver. The pull-up resistor can be connected to a maximum

positive supply of 3.6 V. During a register write operation, the SDA

output driver is high-impedance and the SDA input receiver should

be driven by a driver capable driving the input pin capacitance of

0.8 pF at the 200 kHz maximum SDA frequency. A driver output

impedance less than 20 kΩ is recommended.

Figure 38. Simplified SDA Interface

Figure 39 shows the SCL interface for the serial clock input to the

I2C controller. This input is high impedance and should be driven by

a driver capable of driving the input pin capacitance of 0.8 pF at the

400 kHz maximum SCL frequency. A driver output impedance less

than 10 kΩ is recommended.

Figure 39. Simplified SCL Interface