TPA3003D2

SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003

23

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APPLICATION INFORMATION

is reconfigured as equation 7.

C

1

2

pZ

lowest gain step intended for use in the system. A further consideration for this capacitor is the leakage path

creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain

applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized

capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as

the dc level there is held at 2.5 V, which is likely higher than the source dc level. Note that it is important to confirm

the capacitor polarity in the application.

The TPA3003D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling

to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also

prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is

achieved by using two capacitors of different types that target different types of noise on the power supply leads.

For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance

(ESR) ceramic capacitor, typically 0.1

filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10

µF or greater placed near

the audio power amplifier is recommended. The 10-

µF capacitor also serves as a local storage capacitor for

supplying current during large signal transients on the amplifier outputs.

BSN and BSP capacitors

The full H-bridge output stages use only NMOS transistors. They therefore require bootstrap capacitors for the

high side of each output to turn on correctly. A 10-nF ceramic capacitor, rated for at least 25 V, must be connected

from each output to its corresponding bootstrap input. Specifically, one 10-nF capacitor must be connected from

xOUTP to xBSP, and one 10-nF capacitor must be connected from xOUTN to xBSN. (See the application circuit

diagram in Figure 21.)

VCLAMP capacitors

To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, two

internal regulators clamp the gate voltage. Two 1-

µF capacitors must be connected from VCLAMPL (pin 25)

and VCLAMPR (pin 36) to ground and must be rated for at least 25 V. The voltages at the VCLAMP terminals

preamplifier, and volume control circuitry. It requires a 0.1-

µF to 1-µF capacitor, placed very close to the pin,

to ground to keep the regulator stable. The regulator may not be used to power any external circuitry.

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