M48T86PC1F datasheet(18/36 Pages) STMICROELECTRONICS

18 / 36 page

Clock operations

M48T86

18/36

should avoid interrupt service routines that would cause the time needed to read valid

time/calendar data to exceed 244µs.

The third method uses a periodic interrupt to determine if an update cycle is in progress.

The UIP Bit is set high between the setting of the PF Bit (Register C; Bit 6). Periodic

interrupts that occur at a rate greater than tBUC allow valid time and date information to be

reached at each occurrence of the periodic interrupt.The READs should be completed

within 1/(tPL/2 + tBUC) to ensure that data is not read during the update cycle.

Square wave output selection

Thirteen of the 15 divider taps are made available to a 1-of-15 selector, as shown in the

block diagram of Figure 4 on page 8. The purpose of selecting a divider tap is to generate a

square wave output signal on the SQW pin. The RS3-RS0 bits in Register A establish the

square wave output frequency. These frequencies are listed in Table 4 on page 18. The

SQW frequency selection shares the 1-of-15 selector with the periodic interrupt generator.

Once the frequency is selected, the output of the SQW pin can be turned on and off under

program control with the Square Wave Enabled (SQWE) Bit.

Table 4.

Square wave frequency/periodic interrupt rate

Square wave

Periodic interrupt

RS3

RS2

RS1

RS0

Frequency

Units

Period

Units

0000

None

0001

256

3.90625

0010

128

7.8125

0011

8.192

kHz

122.070

0100

4.096

kHz

244.141

0101

2.048

kHz

488.281

0110

1.024

kHz

976.5625

0111

512

1.953125

1000

256

3.90625

1001

128

7.8125

1010

15.625

1011

31.25

1100

62.5

1101

125

1110

250

1111

500

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