M48T86

Clock operations

19/36

Register A

UIP update in progress

The Update in Progress (UIP) Bit is a status flag that can be monitored. When the UIP Bit is

'1,' the update transfer will soon occur (see Figure 9). When UIP is a '0,' the update transfer

will not occur for at least 244µs. The time, calendar, and alarm information in RAM is fully

available for access when the UIP Bit is '0.' The UIP Bit is “Read only” and is not affected by

RST. Writing the SET Bit in Register B to a '1' inhibits any update transfer and clears the

UIP Status Bit.

OSC0, OSC1, OSC2 oscillator control

These three bits are used to control the oscillator and reset the countdown chain. A pattern

of “010” enables operation by turning on the oscillator and enabling the divider chain. A

pattern of 11X turns the oscillator on, but keeps the frequency divider disabled. When “010”

is written, the first update begins after 500ms.

RS3, RS2, RS1, RS0

These four rate-selection bits select one of the 13 taps on the 15-stage divider or disable the

divider output. The tap selected may be used to generate an output square wave (SQW pin)

and/or a periodic interrupt. The user may do one of the following:

1.

Enable the interrupt with the PIE Bit;

or

2.

Enable the SQW output with the SQWE Bit;

or

3.

Enable both at the same time and same rate;

or

4.

Enable neither.

Table 4 on page 18 lists the periodic interrupt rates and the square wave frequencies that

may be chosen with the RS Bits. These four READ/WRITE bits are not affected by RST.

Table 5.

Register A MSB

Figure 9.

Update period timing and UIP

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

UIP

OSC2

OSC1

OSC0

RS3

RS2

RS1

RS0

AI01651

UIP

UPDATE PERIOD (1sec)

tBUC

tUC