DAP005

Application information

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A second communication line can be established via the disable function included in the

PFC_OK pin (Section 6.2 on page 18 for more details ). Typically this line is used to allow

the PWM controller of the cascaded DC-DC converter to shut down the DAP005 in case of

light load, to minimize the no-load input consumption. Should the residual consumption of

the chip be an issue, it is also possible to cut down the supply voltage. Interface circuits like

those shown in Figure 43, can be used. Needless to say, this operation assumes that the

cascaded DC-DC converter stage works as the master and the PFC stage as the slave or, in

other words, that the DC-DC stage starts first, it powers both controllers and

enables/disables the operation of the PFC stage.

The third communication line is the PWM_STOP pin (pin 9), which works in conjunction with

the AC_OK pin (pin 10). The purpose of the PWM_STOP pin is to inhibit the PWM activity of

both the PFC stage and the cascaded DC-DC converter. The pin is an open collector,

normally open, that goes low if the device is disabled by a voltage lower than 0.52V on the

AC_OK pin. It is important to point out that this function works correctly in systems where

the PFC stage is the master and the cascaded DC-DC converter is the slave or, in other

words, where the PFC stage starts first, powers both controllers and enables/disables the

operation of the DC-DC stage.

Figure 43. Interface circuits that let DC-DC converter’s controller IC disable the DAP005 at light

load

DAP015

PFC_STOP

14

DAP005

(AC_OK)

PFC_OK

7

(10)

DAP01A

PFC_STOP

14

16

Vcc

10 k

Ω

BC557

2.2 k

Ω

DAP005

Vcc

14

8.2 V

DAP005

PFC_OK

BC547

DAP01A

14 PFC_STOP

7

(10)

2.2 k

Ω

8

VREF

100 k

Ω

(AC_OK)