CS5211

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9

the design must first predict the MOSFET power dissipation.

Once the dissipation is known, the heat sink thermal

impedance can be calculated to prevent the specified

maximum case or junction temperatures from being exceeded

at the highest ambient temperature. Power dissipation has two

primary contributors: conduction losses and switching losses.

The control or upper MOSFET will display both switching

and conduction losses. The synchronous or lower MOSFET

will exhibit only conduction losses because it switches into

nearly zero voltage. However, the body diode in the

synchronous MOSFET will suffer diode losses during the

non−overlap time of the gate drivers.

For the upper or control MOSFET, the power dissipation

can be approximated from:

PD,CONTROL + (IRMS,CNTL2 @ RDS(on))

) (ILo,MAX @ Qswitch Ig @ VIN @ fSW)

) (Qoss 2 @ VIN @ fSW) ) (VIN @ QRR @ fSW)

The first term represents the conduction or IR losses when

the MOSFET is ON while the second term represents the

switching losses. The third term is the losses associated with

the control and synchronous MOSFET output charge when

the control MOSFET turns ON. The output losses are caused

by both the control and synchronous MOSFET but are

dissipated only in the control FET. The fourth term is the loss

due to the reverse recovery time of the body diode in the

synchronous MOSFET. The first two terms are usually

adequate to predict the majority of the losses.

current in the control MOSFET:

IRMS,CNTL + D @ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN

) ILo,MIN2) 3]1 2

ILo,MAX + IO,MAX 2 ) DILo 2

ILo,MIN + IO,MAX 2 * DILo 2

D is the duty cycle of the converter:

D + VOUT VIN

inductor of value Lo:

DILo + (VIN * VOUT) @ D (Lo @ fSW)

applied gate drive voltage.

gate−to−source charge plus the gate−to−drain charge. This

may be specified in the data sheet or approximated from the

gate−charge curve as shown in the Figure 5.

Qswitch + Qgs2 ) Qgd

Figure 5. MOSFET Switching Characteristics

Commonly specified in the data sheet.

sheet.

For the lower or synchronous MOSFET, the power

dissipation can be approximated from:

PD,SYNCH + (IRMS,SYNCH2 @ RDS(on))

) (Vfdiode @ IO,MAX 2 @ t_nonoverlap @ fSW)

The first term represents the conduction or IR losses when

the MOSFET is ON and the second term represents the diode

losses that occur during the gate non−overlap time.

All terms were defined in the previous discussion for the

control MOSFET with the exception of:

IRMS,SYNCH + 1 * D

@ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2) 3]1 2

where:

diode at the converter output current.

t_nonoverlap is the non−overlap time between the upper

and lower gate drivers to prevent cross conduction. This

time is usually specified in the data sheet for the control

IC.

When the MOSFET power dissipations are known, the

designer can calculate the required thermal impedance to

maintain a specified junction temperature at the worst case

ambient operating temperature

qT t (TJ * TA) PD

where;

MOSFET.