CS51033GD8 datasheet(5/10 Pages) ONSEMI

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CS51033

http://onsemi.com

CIRCUIT DESCRIPTION

THEORY OF OPERATION

Control Scheme

The CS51033 monitors the output voltage to determine

when to turn on the P−Ch FET. If VFB falls below the internal

reference voltage of 1.25 V during the oscillator’s charge

cycle, the P−Ch FET is turned on and remains on for the

duration of the charge time. The P−Ch FET gets turned off

and remains off during the oscillator’s discharge cycle time

with the maximum duty cycle to 80%. It requires 7.0 mV

typical, and 20 mV maximum ripple on the VFB pin to

operate. This method of control does not require any loop

stability compensation.

Startup

The CS51033 has an externally programmable Soft−Start

feature that allows the output voltage to come up slowly,

preventing voltage overshoot on the output.

At startup, the voltage on all pins is zero. As VCC rises, the

VC voltage along with the internal resistor RG keeps the

P−Ch FET off. As VCC and VC continue to rise, the oscillator

capacitor (COSC ) and the Soft−Start/Fault Timing capacitor

(CS) charges via internal current sources. COSC gets charged

by the current source IC and CS gets charged by the IT source

combination described by:

ICS + IT *

)

The internal Holdoff Comparator ensures that the external

P−Ch FET is off until VCS > 0.7 V, preventing the GATE

flip−flop (F2) from being set. This allows the oscillator to

reach its operating frequency before enabling the drive

output. Soft−Start is obtained by clamping the VFB

comparator’s (A6) reference input to approximately 1/2 of

the voltage at the CS pin during startup, permitting the

control loop and the output voltage to slowly increase. Once

the CS pin charges above the Holdoff Comparator trip point

of 0.7 V, the low feedback to the VFB Comparator sets the

GATE flip−flop during COSC’s charge cycle. Once the

GATE flip−flop is set, VGATE goes low and turns on the

P−Ch FET. When VCS exceeds 2.4 V, the CS charge sense

comparator (A4) sets the VFB comparator reference to 1.25

V completing the startup cycle.

Lossless Short Circuit Protection

The CS51033 has “lossless” short circuit protection since

there is no current sense resistor required. When the voltage

at the CS pin (the fault timing capacitor voltage ) reaches

2.5 V, the fault timing circuitry is enabled. During normal

operation the CS voltage is 2.6 V. During a short circuit or

a transient condition, the output voltage moves lower and the

voltage at VFB drops. If VFB drops below 1.15 V, the output

of the fault comparator goes high and the CS51033 goes into

a fast discharge mode. The fault timing capacitor, CS,

discharges to 2.4 V. If the VFB voltage is still below 1.15 V

when the CS pin reaches 2.4 V, a valid fault condition has

been detected. The slow discharge comparator output goes

high and enables gate G5 which sets the slow discharge

flip−flop. The VGATE flip−flop resets and the output switch

is turned off. The fault timing capacitor is slowly discharged

to 1.5 V. The CS51033 then enters a normal startup routine.

If the fault is still present when the fault timing capacitor

voltage reaches 2.5 V, the fast and slow discharge cycles

repeat as shown in Figure 3.

If the VFB voltage is above 1.15 V when CS reaches 2.4 V

a fault condition is not detected, normal operation resumes

and CS charges back to 2.6 V. This reduces the chance of

erroneously detecting a load transient as a fault condition.

Figure 3. Voltage on Start Capacitor (VGS), the Gate (VGATE), and in the Feedback Loop (VFB),

During Startup, Normal and Fault Conditions

1.15 V

1.25 V

0 V

1.5 V

2.4 V

2.6 V

2.5 V

0 V

VCS

VGATE

VFB

START

NORMAL OPERATION

FAULT

td1

TSTART

tFAULT

tRESTART td2

tFAULT

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