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CS51033

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6) Divider Bypass Capacitor CRR

Since the feedback resistors divide the output voltage by

a factor of 4.0, i.e. 5.0 V/1.25 V= 4.0, it follows that the

output ripple is also divided by four. This would require that

the output ripple be at least 60 mV (4.0

× 15 mV) to trip the

feedback comparator. We use a capacitor CRR to act as an

AC short so that the output ripple is not attenuated by the

divider network. The ripple voltage frequency is equal to the

switching frequency so we choose CRR so that:

XC +

1.0

pfC

is negligible at the switching frequency.

In this case FSW is 200 kHz if we allow XC = 3.0 W then:

+ 1.0

pf3 ^

0.265

7) Soft−Start and Fault Timing Capacitor CS

CS performs several important functions. First it provides

a dead time for load transients so that the IC does not enter

a fault mode every time the load changes abruptly. Secondly

it disables the fault circuitry during startup, it also provides

Soft−Start by clamping the reference voltage during startup

to rise slowly and finally it controls the hiccup short circuit

protection circuitry. This function reduces the P−Ch FET’s

duty cycle to 2.0% of the CS period.

The most important consideration in calculating CS is that

it’s voltage does not reach 2.5 V (the voltage at which the

fault detect circuitry is enabled) before VFB reaches 1.15 V

otherwise the power supply will never start.

If the VFB pin reaches 1.15 V, the fault timing comparator

will discharge CS and the supply will not start. For the VFB

voltage to reach 1.15 V the output voltage must be at least

× 1.15 = 4.6 V.

If we choose an arbitrary startup time of 200

ms, we

calculate the value of CS from:

+ CS

2.5 V

ICHARGE

CS(MIN) +

200

264

2.5 V

+ 0.02 mF

Use 0.1

mF.

The fault time out time is the sum of the slow discharge

time the fast discharge time and the recharge time and is

obviously dominated by the slow discharge time.

The first parameter is the slow discharge time, it is the time

for the CS capacitor to discharge from 2.4 V to 1.5 V and is

given by:

TSLOWDISCHARGE +

(2.4 V

* 1.5 V)

IDISCHARGE

where IDISCHARGE is 6.0 mA typical.

TSLOWDISCHARGE + CS

1.5 V

105

The fast discharge time occurs when a fault is first

detected. The CS capacitor is discharged from 2.5 V to 2.4 V.

TFASTDISCHARGE +

(2.5 V

* 2.4 V)

IFASTDISCHARGE

where IFASTDISCHARGE is 66 mA typical.

TFASTDISCHARGE + CS

1515

The recharge time is the time for CS to charge from 1.5 V

to 2.5 V.

TCHARGE +

(2.5 V

* 1.5 V)

ICHARGE

where ICHARGE is 264 mA typical.

TCHARGE + CS

3787

The fault time out time is given by:

TFAULT + CS

(3787

) 1515 ) 1.5

105)

TFAULT + CS

(1.55

105)

For this circuit

TFAULT + 0.1

10*6

1.55

105

+ 0.0155

A larger value of CS will increase the fault time out time

but will also increase the Soft−Start time.

8) Input Capacitor

The input capacitor reduces the peak currents drawn from

the input supply and reduces the noise and ripple voltage on

the VCC and VC pins. This capacitor must also ensure that

the VCC remains above the UVLO voltage in the event of an

output short circuit. CIN should be a low ESR capacitor of

at least 100

mF. A ceramic surface mount capacitor should

also be connected between VCC and ground to prevent

spikes.

9) MOSFET Selection

The CS51033 drives a P−Channel MOSFET. The VGATE

pin swings from GND to VC. The type of P−Ch FET used

depends on the operating conditions but for input voltages

below 7.0 V a logic level FET should be used.

Choose a P−Ch FET with a continuous drain current (ID)

rating greater than the maximum output current. RDS(ON)

should be less than

RDS t+

0.6 V

IOUT(MAX)

167 m

The

Gate−to−Source

voltage

VGS

and

the

Drain−to−Source Breakdown Voltage should be chosen

based on the input supply voltage.

The power dissipation due to the conduction losses is

given by:

PD + IOUT2

RDS(ON)

The power dissipation due to the switching losses is given

by:

PD + 0.5

VIN

IOUT

(TRr ) TF)

FSW

where TR = Rise Time and TF = Fall Time.

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