ST72F262G2B6 datasheet(103/172 Pages) STMICROELECTRONICS

103 / 172 page

ST72260Gx, ST72262Gx, ST72264Gx

103/172

11.6 I2C BUS INTERFACE (I2C)

11.6.1 Introduction

The I2C Bus Interface serves as an interface be-

tween the microcontroller and the serial I2C bus. It

provides both multimaster and slave functions,

and controls all I2C bus-specific sequencing, pro-

tocol, arbitration and timing. It supports fast I2C

mode (400kHz).

11.6.2 Main Features

■ Parallel-bus/I

2C protocol converter

■ Multi-master capability

■ 7-bit/10-bit Addressing

■ SMBus V1.1 Compliant

■ Transmitter/Receiver flag

■ End-of-byte transmission flag

■ Transfer problem detection

I2C Master Features:

■ Clock generation

■ I

2C bus busy flag

■ Arbitration Lost Flag

■ End of byte transmission flag

■ Transmitter/Receiver Flag

■ Start bit detection flag

■ Start and Stop generation

I2C Slave Features:

■ Stop bit detection

■ I

2C bus busy flag

■ Detection of misplaced start or stop condition

■ Programmable I

2C Address detection

■ Transfer problem detection

■ End-of-byte transmission flag

■ Transmitter/Receiver flag

11.6.3 General Description

In addition to receiving and transmitting data, this

interface converts it from serial to parallel format

and vice versa, using either an interrupt or polled

handshake. The interrupts are enabled or disabled

by software. The interface is connected to the I2C

bus by a data pin (SDAI) and by a clock pin (SCLI).

It can be connected both with a standard I2C bus

and a Fast I2C bus. This selection is made by soft-

ware.

Mode Selection

The interface can operate in the four following

modes:

– Slave transmitter/receiver

– Master transmitter/receiver

By default, it operates in slave mode.

The interface automatically switches from slave to

master after it generates a START condition and

from master to slave in case of arbitration loss or a

STOP generation, allowing then Multi-Master ca-

pability.

Communication Flow

In Master mode, it initiates a data transfer and

generates the clock signal. A serial data transfer

always begins with a start condition and ends with

a stop condition. Both start and stop conditions are

generated in master mode by software.

In Slave mode, the interface is capable of recog-

nising its own address (7 or 10-bit), and the Gen-

eral Call address. The General Call address de-

tection may be enabled or disabled by software.

Data and addresses are transferred as 8-bit bytes,

MSB first. The first byte(s) following the start con-

dition contain the address (one in 7-bit mode, two

in 10-bit mode). The address is always transmitted

in Master mode.

A 9th clock pulse follows the 8 clock cycles of a

byte transfer, during which the receiver must send

an acknowledge bit to the transmitter. Refer to Fig-

ure 57.

Figure 57. I2C BUS Protocol

SCL

SDA

MSB

ACK

STOP

START

CONDITION

VR02119B

ST72F262G2B6 数据表(PDF) 103 Page - STMicroelectronics

ST72F262G2B6 数据表(HTML) 103 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载