ST72F262G2B6 datasheet(47/172 Pages) STMICROELECTRONICS

47 / 172 page

ST72260Gx, ST72262Gx, ST72264Gx

47/172

MISCELLANEOUS REGISTERS (Cont’d)

MISCELLANEOUS REGISTER 2 (MISCR2)

Read/Write

Reset Value: 0000 0000 (00h)

Caution: This register has been provided for com-

patibility with the ST72254 family only. The same

bits are available in the SPICSR register. New ap-

plications must use the SPICSR register. Do not

use both registers, this will cause the SPI to mal-

function.

Bits 7:4 = Reserved always read as 0

Bits 3 = MOD SPI Master Output Disable

This bit is set and cleared by software. When set, it

disables the SPI Master (MOSI) output signal.

0: SPI Master Output enabled.

1: SPI Master Output disabled.

Bit 2 = SOD SPI Slave Output Disable

This bit is set and cleared by software. When set it

disable the SPI Slave (MISO) output signal.

0: SPI Slave Output enabled.

1: SPI Slave Output disabled.

Bit 1 = SSM SS mode selection

This bit is set and cleared by software.

0: Normal mode - the level of the SPI SS signal is

input from the external SS pin.

1: I/O mode, the level of the SPI SS signal is read

from the SSI bit.

Bit 0 = SSI SS internal mode

This bit replaces the SS pin of the SPI when the

SSM bit is set to 1. (see SPI description). It is set

and cleared by software.

Table 11. Miscellaneous Register Map and Reset Values

MOD SOD

SSM

SSI

Address

(Hex.)

Label

76543

210

0020h

MISCR1

Reset Value

IS11

IS10

MCO

IS01

IS00

CP1

CP0

SMS

0040h

MISCR2

Reset Value

0000

MOD

SOD

SSM

SSI

ST72F262G2B6 数据表(PDF) 47 Page - STMicroelectronics

ST72F262G2B6 数据表(HTML) 47 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载