ST72F262G2B6 datasheet(27/172 Pages) STMICROELECTRONICS

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.4 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)

Read/Write

Reset Value: 000x 000x (00h)

Bit 7 = Reserved, always read as 0.

Bit 6 = AVDIE Voltage Detector interrupt enable

This bit is set and cleared by software. It enables

an interrupt to be generated when the AVDF flag

changes (toggles). The pending interrupt informa-

tion is automatically cleared when software enters

the AVD interrupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

Bit 5 = AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware.

If the AVDIE bit is set, an interrupt request is gen-

erated when the AVDF bit changes value.

0: VDD over VIT+(AVD) threshold

1: VDD under VIT-(AVD) threshold

Bit 4 = LVDRF LVD reset flag

This bit indicates that the last Reset was generat-

ed by the LVD block. It is set by hardware (LVD re-

set) and cleared by software (writing zero). See

WDGRF flag description for more details. When

the LVD is disabled by OPTION BYTE, the LVDRF

bit value is undefined.

Bit 3:1 = Reserved, must be kept cleared.

Bit 0 = WDGRF Watchdog reset flag

This bit indicates that the last Reset was generat-

ed by the Watchdog peripheral. It is set by hard-

ware (watchdog reset) and cleared by software

(writing zero) or an LVD Reset (to ensure a stable

cleared state of the WDGRF flag when CPU

starts).

Combined with the LVDRF flag information, the

flag description is given by the following table.

Application Notes

The LVDRF flag is not cleared when another RE-

SET type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the origi-

nal failure. In this case, a watchdog reset can be

detected by software while an external reset can

not.

AVD

LVD

000

WDG

RESET Sources

LVDRF

WDGRF

External RESET pin

Watchdog

LVD

Address

(Hex.)

Label

76543

210

0025h

SICSR

Reset Value

AVDIE

AVDF

LVDRF

WDGRF

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