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PSD835G2 数据表(PDF) 49 Page - STMicroelectronics |
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PSD835G2 数据表(HTML) 49 Page - STMicroelectronics |
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49 / 102 page ![]() 49/102 PSD835G2 External Chip The CPLD also provides eight Chip Select outputs that can be used to select external devices. The Chip Selects can be routed to either Port C or Port F, depending on the pin declaration in the PSD- soft. Each Chip Select (ECS0-ECS7) consists of one product term that can be configured active High or Low. The Output Enable of the pin is controlled by either the Output Enable product term or the Direction Register (See Figure 19). Figure 19. External Chip Select POLARITY BIT PD0 PIN ECS PT ECS TO PORT C OR F ENABLE (.OE) PT DIRECTION REGISTER AI07654 PORT C OR PORT F |
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