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ES9039MSPRO 数据表(PDF) 41 Page - ESS Technology,Inc |
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ES9039MSPRO 数据表(HTML) 41 Page - ESS Technology,Inc |
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41 / 95 page  ES9039MPRO & ES9039PRO Datasheet CONFIDENTIAL ADVANCE INFORMATION 0.2.1 41 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM Register 1: SYS MODE CONFIG Bits [7] [6] [5:4] [3] [2] [1] [0] Default 1'b1 1'b0 2'b11 1'b0 1'b0 1'b0 1'b1 Bits Mnemonic Description [7] ENABLE_DAC_CLK Enables DAC interpolation path clock. • 1'b0: Clock disabled • 1'b1: Clock enabled (default) [6] SYNC_MODE Enables SYNC mode • 1'b0: ASYNC mode enabled (default) • 1'b1: SYNC mode enabled [5:4] RESERVED NA [3] ENABLE_SPDIF_DECODE Enables S/PDIF decoding. • 1'b0: Disabled (default) • 1'b1: Enabled [2] ENABLE_DOP_DECODE Enables DoP decoding. • 1'b0: Disabled (default) • 1'b1: Enabled [1] ENABLE_DSD_DECODE Enables DSD decoding. • 1'b0: Disabled (default) • 1'b1: Enabled [0] ENABLE_TDM_DECODE Enables TDM decoding. • 1'b0: Disabled (default) • 1'b1: Enabled Register 2: RESERVED Register 3: DAC CLOCK CONFIG Bits [7] [6] [5:0] Default 1'b1 1'b0 6'd0 Bits Mnemonic Description [7] AUTO_FS_DETECT • 1'b0: Disabled • 1'b1: Auto tune CLK_DAC/CLK_IDAC ratio according to detected FS (default) Note: Cannot be used in ASYNC mode [6] SELECT_IDAC_HALF • 1'b0: Divide by SELECT_IDAC_NUM + 1 (default) • 1'b1: Divide by half of SELECT_IDAC_NUM + 1 Note: Can only produce half of an odd number divide [5:0] SELECT_IDAC_NUM CLK_IDAC divider. Whole number divide value + 1 for CLK_IDAC (SYS_CLK/divide_value). • 6'd0: Whole number divide value + 1 = 1 • 6'd1: Whole number divide value + 1 = 2 • 6'd63: Whole number divide value + 1 = 64 |
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