ADFS7124-8BBCPZ datasheet(46/93 Pages) AD

46 / 93 page

Data Sheet

ADFS7124-8

ADC CIRCUIT INFORMATION

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Rev. 0 | 46 of 93

ANALOG INPUT CHANNEL

The uses flexible multiplexing; thus, any of the analog input pins,

AIN0 to AIN15, can be selected as a positive or negative input. This

feature allows the user to perform diagnostics such as checking

that pins are connected. It also simplifies printed circuit board

(PCB) design. For example, the same PCB can accommodate

2-wire, 3-wire, and 4-wire resistance temperature detectors (RTDs).

AIN0

AIN1

AVDD

AVSS

AVDD

AVSS

AIN14

AVDD

AIN15

AVDD

AVSS

PGA

TO ADC

BURNOUT

CURRENTS

Figure 73. Analog Input Multiplexer Circuit

The channels are configured using the AINP[4:0] bits and the

AINM[4:0] bits in the channel registers (see Table 48). The device

can be configured to have 8 differential inputs, 15 pseudo differ-

ential inputs, or a combination of both. When using differential

inputs, use adjacent analog input pins to form the input pair. Using

adjacent pins minimizes any mismatch between the channels.

The inputs can be buffered or unbuffered at a gain of 1 but are

automatically buffered when the gain exceeds 1. The AINP and

AINM buffers are enabled/disabled separately using the AIN_BUFP

and AIN_BUFM bits in the configuration register (see Table 49).

In buffered mode, the input channel feeds into a high impedance

input stage of the buffer amplifier. Therefore, the input can tolerate

significant source impedances and is tailored for direct connection

to external resistive type sensors such as strain gages or RTDs.

When the device is operated in unbuffered mode, the device has

a higher analog input current. Note that this unbuffered input path

provides a dynamic load to the driving source. Therefore, resis-

tor/capacitor (RC) combinations on the input pins can cause gain

errors, depending on the output impedance of the source driving

the ADC input.

The absolute input voltage in unbuffered mode (gain = 1) includes

the range between AVSS − 50 mV and AVDD + 50 mV. The absolute

input voltage range in buffered mode at a gain of 1 is restricted

to a range between AVSS + 100 mV and AVDD − 100 mV. The

common-mode voltage must not exceed these limits; otherwise,

linearity and noise performance degrade.

When the gain is greater than 1, the analog input buffers are

automatically enabled. The PGA placed in front of the input buffers

is rail-to-rail; thus, in this case, the absolute input voltage includes

the range from AVSS − 50 mV to AVDD + 50 mV.

Table 48. Channel Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x09 to

0x18

CHANNEL_0 to

CHANNEL_15

[15:8] Enable

Setup

AINP[4:3]

0x8001 RW

[7:0]

AINP[2:0]

AINM[4:0]

Table 49. Configuration Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x19 to

0x20

CONFIG_0 to

CONFIG_7

[15:8]

Bipolar

Burnout

REF_BUFP

0x0860 RW

[7:0]

REF_BUFM AIN_BUFP

AIN_BUFM

REF_SEL

PGA

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