AM68 datasheet(2/253 Pages) TI1

2 / 253 page

• One USB 3.0 dual-role device (DRD) subsystem

– Enhanced SuperSpeed Gen1 Port

– Supports Type-C switching

– Independently configurable as USB host, USB

peripheral, or USB DRD

• Two CSI2.0 4L RX plus Two CSI2.04L TX

• Two Ethernet RMII/RGMII interfaces

Flash memory interfaces:

• Embedded MultiMediaCard Interface (eMMC™ 5.1)

• One Secure Digital® 3.0/Secure Digital Input

Output 3.0 interfaces (SD3.0/SDIO3.0)

• Two simultaneous flash interfaces configured as

– One OSPI or HyperBus™ or QSPI, and

– One QSPI

Technology / Package:

• 16-nm FinFET technology

• 23 mm x 23 mm, 0.8-mm pitch, 770-pin FCBGA

(ALZ)

2 Applications

• Machine Vision Camera and computers

• Smart shopping cart

• Retail automation

• Smart agriculture

• Video surveillance

• Traffic monitoring

• Autonomous Mobile Robots (AMR)

• Drone

• Industrial transport

• Industrial Human Machine Interfaces (HMI)

• Industrial PC

• Single board computers

• Patient monitoring and medical devices

3 Description

The AM68 scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart

Vision Camera and General Compute applications and built on extensive market knowledge accumulated over

a decade of TI’s leadership in the Vision processor market. The AM68x family is built for a broad set of

cost-sensitive high-performance compute applications in Factory Automation, Building Automation, and other

markets.

The AM68 provides high performance compute technology for both traditional and deep learning algorithms

at industry leading power/performance ratios with a high level of system integration to enable scalability and

lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for

general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional

algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU

island. All protected by industrial-grade safety and security hardware accelerators.

General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm®

Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to two Arm®

Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72

core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes

flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics

applications. Integrated diagnostics and safety features support operations up to SIL-2 levels while the

integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs.

Key Performance Cores Overview: The C7000™ DSP next generation core (“C7x”) combines TI’s industry

leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation

capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new

“MMA” deep learning accelerator enables performance up to 8 Trillion Operations Per Second (TOPS) within

the lowest power envelope in the industry even when operating even at the worst case junction temperatures

of 105°C and 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact

on system performance. The C7x/MMA cores are available only for deep learning function in the AM68 class of

processors.

AM68A, AM68

SPRSP91A – FEBRUARY 2023 – REVISED AUGUST 2023

www.ti.com

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