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AM68 数据表(PDF) 7 Page - Texas Instruments |
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AM68 数据表(HTML) 7 Page - Texas Instruments |
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7 / 253 page  Table 5-1. Device Comparison (continued) FEATURES(7) REFERENCE NAME AM68A9 AM68A7 AM685 AM683 Inter-Integrated Circuit Interface I2C 10 Improved Inter-Integrated Circuit Interface I3C 1 Analog-to-Digital Converter ADC 2 Capture Subsystem with Camera Serial Interface (CSI2) CSI2.0 4L RX 2 CSI2.0 4L TX 2 Multichannel Serial Peripheral Interface MCSPI 11 Multichannel Audio Serial Port MCASP0 16 Serializers MCASP1 5 Serializers MCASP2 5 Serializers MCASP3 3 Serializers MCASP4 5 Serializers MultiMedia Card/ Secure Digital Interface MMCSD0 eMMC (8-bits) MMCSD1 SD/SDIO (4-bits) Universal Flash Storage UFS 2L No Flash Subsystem (FSS) OSPI0 8-bits(6) OSPI1(8) 4-bits HyperBus Yes(6) 4x PCI Express Port with Integrated PHY PCIE0 Up to Four Lanes(5) Hyperlink HYP No(9) Gigabit Ethernet Interface MCU 1x RGMII or RMII Main 1x RGMII or RMII General-Purpose Timers TIMER 30 Enhanced High Resolution Pulse- Width Modulator Module eHRPWM 6 Enhanced Capture Module eCAP 3 Enhanced Quadrature Encoder Pulse Module eQEP 3 Universal Asynchronous Receiver and Transmitter UART 12 Universal Serial Bus (USB3.1) SuperSpeed Dual-Role-Device (DRD) Ports with SS PHY USB0 Yes(5) (1) Functional Safety is not supported on this device family, if interested in this feature, please see the TDA4VE device family. (2) Device security features including Secure Boot and Customer Programmable Keys are applicable to select part number variants as indicated by the Device Type (Y) identifier in the Table 10-1, Nomenclature Description table (3) AEC-Q100 qualification is applicable to select part number variants as indicated by the Automotive Designator (Q1) identifier in the Table 10-1, Nomenclature Description table (4) DDRSS0 and DDRSS1 must always be used in incremental order. For instance, when using a single LPDDR component, it must beconnected to the DDR0_* interface. (5) USB3.0 and PCIE share a total of four SerDes lanes. (6) Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus and OSPI1. (7) J721S2 is the base part number for the superset device. Software should constrain the features used to match the intended production device. (8) OSPI1 module only pins out 4 pins and is referred to as QSPI in some contexts. (9) Hyperlink is not supported on this SoC. System designs should not use the signals HYP_*, HYP0_*, HYP1_*. (10) MCU_R5FSS0 includes Dual-Core R5F that provides Device Management functionality, and is reserved for executing TI provided code. R5FSS1 is a Dual-Core R5F that provides Multimedia Control functionality, and is reserved for executing TI provided code. (11) The two C7x DSPs are reserved for executing TI provided code, and are not available for custom code. www.ti.com AM68A, AM68 SPRSP91A – FEBRUARY 2023 – REVISED AUGUST 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: AM68A AM68 |
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