tPHZ

tPLZ

tPZL

tPZH

3 V

0 V

Output

Control

(low-level

enabling)

Waveform 1

(see Notes C

and D)

Waveform 2

(see Notes C

and D)

≈1.5 V

VOH 0.3 V

–

VOL + 0.3 V

≈1.5 V

1.3 V

1.3 V

1.3 V

1.3 V

VOL

VOH

t

tPZH

≈1.5 V

V

VOL

tPHL

tPLH

tPLH

tPHL

Input

Out-of-Phase

Output

(see Note D)

3 V

0 V

VOL

VOH

VOH

VOL

In-Phase

Output

(see Note D)

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

3 V

3 V

0 V

0 V

t

t

h

su

Timing

Input

Data

Input

1.3 V

1.3 V

1.3 V

8

SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244

SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244

SDLS144D – APRIL 1985 – REVISED OCTOBER 2016

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Product Folder Links: SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240

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Copyright © 1985–2016, Texas Instruments Incorporated

Figure 6. Voltage Waveforms,

Setup and Hold Times

Figure 7. Voltage Waveforms,

Propagation Delay Times

A.

CL includes probe and jig capacitance.

B.

All diodes are 1N3064 or equivalent.

C.

Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output

control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the

output control.

D.

S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open

for tPZL.

E.

Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.

F.

All input pulses are supplied by generators having the following characteristics: PRR

≤ 1 MHz, ZO is approximately

50 Ω, tr ≤ 15 ns, tf ≤ 6 ns.

G.

The outputs are measured one at a time with one input transition per measurement.

Figure 8. Voltage Waveforms,

Enable and Disable Times, 3-State Outputs