1

2

4

6

8

19

11

13

15

17

3

5

7

9

12

14

16

18

1A1

1A2

1A3

1A4

1Y1

2A1

2A2

2A3

2A4

2Y1

1Y2

1Y3

1Y4

2Y2

2Y3

2Y4

2G

1G

Copyright © 2016, Texas Instruments Incorporated

1

2

4

6

8

19

11

13

15

17

3

5

7

9

12

14

16

18

1A1

1A2

1A3

1A4

1Y1

2A1

2A2

2A3

2A4

2Y1

1Y2

1Y3

1Y4

2Y2

2Y3

2Y4

2G

1G

Copyright © 2016, Texas Instruments Incorporated

11

SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244

SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244

www.ti.com

SDLS144D – APRIL 1985 – REVISED OCTOBER 2016

Product Folder Links: SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240

SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244

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Copyright © 1985–2016, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

This device is organized as two 4-bit buffers and drivers with separate output-enable (G) inputs. When G is low,

the device passes data from the A inputs to the Y outputs. When G is high, the outputs are in the high

impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device

as a translator in a mixed 3.3-V and 5-V system environment. To ensure the high-impedance state during power

up or power down, G must be tied to VCC through a pullup resistor; the minimum value of the resistor is

determined by the current-sinking capability of the driver.

8.2 Functional Block Diagrams

Pin numbers shown are for DB, DW, J, N,

NS, and W packages

Figure 16. SNx4LS240 and SNx4S240

Logic Diagram

Pin numbers shown are for DB, DW, J, N,

NS, and W packages

Figure 17. SNx4LS241 and SNx4S241

Logic Diagram