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4066-S14-R 数据表(PDF) 5 Page - Unisonic Technologies

部件名 4066-S14-R
功能描述  QUAD BILATERAL SWITCH
PDF  7 Pages
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制造商  UTC [Unisonic Technologies]
网页  http://www.utc-ic.com
标志 UTC - Unisonic Technologies

4066-S14-R 数据表(HTML) 5 Page - Unisonic Technologies

  4066-S14-R Datasheet HTML 1Page - Unisonic Technologies 4066-S14-R Datasheet HTML 2Page - Unisonic Technologies 4066-S14-R Datasheet HTML 3Page - Unisonic Technologies 4066-S14-R Datasheet HTML 4Page - Unisonic Technologies 4066-S14-R Datasheet HTML 5Page - Unisonic Technologies 4066-S14-R Datasheet HTML 6Page - Unisonic Technologies 4066-S14-R Datasheet HTML 7Page - Unisonic Technologies  
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4066
CMOS IC
UNISONICTECHNOLOGIESCO.,LTD
5 of 7
www.unisonic.com.tw
QW-R502-009,C
SPECIAL CONSIDERATIONS
In applications where separate power sources are used to drive VDD and the signal input, the VDD current capability
should exceed VDD/RL (RL=effective external load of the UTC 4066 bilateral switches).This provision avoids any
permanent current flow or clamp action of the VDD supply when power is applied or removed from UTC 4066.
In certain applications, the external load-resistor current may include both VDD and Signal-line components. To
avoid drawing VDD current when switch current flows into terminals 1,4,8 or 11,the voltage drop across the
bidirectional swith must not exceed 0.6V at Ta ≤ 25 ,
℃
or 0.4V at Ta >25℃ (calculated from RON values shown).
NO VDD current will flow through RL if the switch current flows into terminals2, 3, 9 or 10.
AC TEST CIRCUITS AND SWITCHING TIME WAVEFORMS
OU
T
/IN
VC=VDD
VIS
VDD
VOS
RL
200KΩ
CL
50pF
90%
50%
10%
VDD
0V
VDD
0V
VOS
VIS
tf
tf
t
PLN
tPNL
50%
FIGURE 1. t PHL,t PLH Propagation Delay Time Signal Input to Signal Output
CONTROL
VDD
IN/OUT
Vss
1OF 4
SWITCHES
OUT/IN
VC
VDD
VOS
RL
1KΩ
50%
10%
VDD
0V
VOH
0V
tPHZ
FIGURE 2. tPZH, t PHZ Propagation Delay Time Control to Signal Output
VIS=VDD
tPZH
VDD
0V
VOH
0V
50%
90%
VDD
tPZH
tPHZ
CL
50pF
CONTROL
VDD
IN/OUT
OUT/IN
Vss
1 OF 4
SWITCHES
CONTROL
VDD
IN/OUT
OUT/IN
Vss
1OF 4
SWITCHES
VC
VDD
VOS
RL
1KΩ
50%
VDD
0V
VDD
VOL
tPLZ
FIGURE 3 . t PZL, t PLZ Propagation Delay Time Control to Signal Output
VIS=0V
tPZL
VDD
0V
50%
tPZL
tPLZ
VDD
90%
10%
VDD
VOL
CL
50pF
VC
5V
VOS
RL
FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough
VIS
-5V
Vc=VDD for distortion and frequency response tests
Vc= Vss for feedthrough test
CONTROL
VDD
IN/OUT
OUT/IN
Vss
1OF 4
SWITCHES
1/f
2.5V
VIS 0V
-2.5V
=



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