WM8152

Production Data

w

PD Rev 4.2 April 2007

8

INPUT VIDEO SAMPLING

MCLK

VSMP

INPUT

VIDEO

t

PER

t

VSMPSU

t

VSMPH

t

VSU

t

VH

t

RSU

t

RH

t

MCLKL

t

MCLKH

Figure 1 Input Video Timing

Note:

1.

See Page 15 (Programmable VSMP Detect Circuit) for video sampling description.

Test Conditions

°C, MCLK = 24MHz unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

MCLK period

41.6

ns

MCLK high period

18.8

ns

MCLK low period

18.8

ns

VSMP set-up time

6

ns

VSMP hold time

3

ns

Video level set-up time

10

ns

Video level hold time

3

ns

Reset level set-up time

10

ns

Reset level hold time

3

ns

Notes:

1.

2.

Parameters are measured at 50% of the rising/falling edge.

OUTPUT DATA TIMING

MCLK

OP[3:0]

t

PD

t

PD

Figure 2 Output Data Timing

Test Conditions

°C, MCLK = 24MHz unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Output propagation delay

20

ns