WM8152

Production Data

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PD Rev 4.2 April 2007

10

INTERNAL POWER ON RESET CIRCUIT

Figure 4 Internal Power On Reset Circuit Schematic

The WM8152 includes an internal Power-On-Reset Circuit, as shown in Figure 4, which is used to

reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and

monitors DVDD1. It asserts PORB low if AVDD or DVDD1 is below a minimum threshold.

The power supplies can be brought up in any order but is important that either AVDD is brought up

and is stable before DVDD comes up or vice versa as shown in Figure 5 and Figure 6.

Figure 5 Typical Power up Sequence where AVDD is Powered before DVDD1

Figure 5 shows a typical power-up sequence where AVDD is powered up first. When AVDD rises

above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is

asserted low and the chip is held in reset. In this condition, all writes to the control interface are

ignored. Now AVDD is at full supply level. Next DVDD1 rises to Vpord_on and PORB is released

high and all registers are in their default state and writes to the control interface may take place.

On power down, where AVDD falls first, PORB is asserted low whenever AVDD drops below the

minimum threshold Vpora_off.