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数据搜索系统，热门电子元器件搜索 |
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WM8510GEDS/V 数据表(PDF) 48 Page - Wolfson Microelectronics plc |
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WM8510GEDS/V 数据表(HTML) 48 Page - Wolfson Microelectronics plc |
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48 / 81 page  WM8510 Production Data w PD Rev 4.1 December 2006 48 Figure 26 Right Justified Audio Interface (assuming n-bit word length) In I 2S mode, the MSB is available on the second rising edge of BCLK following a FRAME transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. Figure 27 I 2S Audio Interface (assuming n-bit word length) In DSP/PCM mode, the left channel MSB is available on the 2 nd (mode A) rising edge of BCLK (selectable by FRAMEP) following a rising edge of FRAME. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. Figure 28 DSP/PCM Mode Audio Interface (mode A) When using ADCLRSWAP = 1 or DACLRSWAP = 1 in DSP/PCM mode, the data will appear in the Right Phase of the FRAME, which will be 16/20/24/32 bits after the FRAME pulse. |
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