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WM8746SEDS/R 数据表(PDF) 8 Page - Wolfson Microelectronics plc |
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WM8746SEDS/R 数据表(HTML) 8 Page - Wolfson Microelectronics plc |
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8 / 32 page  WM8746 Production Data w March 2006, PD Rev 4.0 8 MASTER CLOCK TIMING SCKI t SCKIL t SCKIH t SCKIY Figure 1 Master Clock Timing Requirements Test Conditions AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25 oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information SCKI System clock pulse width high tSCKIH 13 ns SCKI System clock pulse width low tSCKIL 13 ns SCKI System clock cycle time tSCKIY 26 ns SCKI Duty cycle 40:60 60:40 Table 1 Master Clock Timing Requirements DIGITAL AUDIO INTERFACE TIMING BCLK DACLRC t BCH t BCL t BCY DIN0/1/2 t LRSU t DS t LRH t DH Figure 2 PCM Digital Audio Data Timing Test Conditions AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25 oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCKIN cycle time tBCY 40 ns BCKIN pulse width high tBCH 16 ns BCKIN pulse width low tBCL 16 ns LRCIN set-up time to BCKIN rising edge tLB 8 ns LRCIN hold time from BCKIN rising edge tBL 8 ns DIN0/1/2 set-up time to BCKIN rising edge tDS 8 ns DIN0/1/2 hold time from BCKIN rising edge tDH 8 ns Table 2 PCM Digital Audio Timing |
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