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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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WM8762GED/V 数据表(PDF) 7 Page - Wolfson Microelectronics plc |
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WM8762GED/V 数据表(HTML) 7 Page - Wolfson Microelectronics plc |
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7 / 15 page  WM8762 Production Data w PD Rev 4.2 July 2006 7 MASTER CLOCK TIMING MCLK t MCLKL t MCLKH t MCLKY Figure 1 Master Clock Timing Requirements Test Conditions VDD = 5V, GND = 0V, TA = +25 oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information MCLK Master clock pulse width high tMCLKH 8 ns MCLK Master clock pulse width low tMCLKL 8 ns MCLK Master clock cycle time tMCLKY 20 ns MCLK Duty cycle 40:60 60:40 Time from MCLK stopping to power down. 1.5 12 µs DIGITAL AUDIO INTERFACE BCKIN LRCIN t BCH t BCL t BCY DIN t LRSU t DS t LRH t DH Figure 2 Digital Audio Data Timing Test Conditions VDD = 5V, GND = 0V, TA = +25 oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCKIN cycle time tBCY 40 ns BCKIN pulse width high tBCH 16 ns BCKIN pulse width low tBCL 16 ns LRCIN set-up time to BCKIN rising edge tLRSU 8 ns LRCIN hold time from BCKIN rising edge tLRH 8 ns DIN set-up time to BCKIN rising edge tDS 8 ns DIN hold time from BCKIN rising edge tDH 8 ns |
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