WM8762

Production Data

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PD Rev 4.2 July 2006

9

CLOCKING SCHEMES

In a typical digital audio system there is only one central clock source producing a reference

clock to which all audio data processing is synchronised. This clock is often referred to as the

audio system’s Master Clock. The external master clock can be applied directly through the

MCLK input pin with no configuration necessary for sample rate selection.

Note that on the WM8762, MCLK is used to derive clocks for the DAC path. The DAC path

consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing.

In a system where there are a number of possible sources for the reference clock it is

recommended that the clock source with the lowest jitter be used to optimise the performance

of the DAC.

The device can be powered down by stopping MCLK. In this state the power consumption is

substantially reduced.

DIGITAL AUDIO INTERFACE

WM8762 supports the left justified audio interface format. The WM8762 supports word lengths

of 16-24 bits (MSB first). The word length may be any value up to 24-bits. (If the word length

shorter than 24-bits is used, the unused bits will be padded with zeros).

In left justified mode, the MSB of DIN is sampled by the WM8762 on the first rising edge of

BCKIN following a LRCIN transition. LRCIN is high during the left samples and low during the

right samples.

Figure 3 Left Justified Mode Timing Diagram

AUDIO DATA SAMPLING RATES

The master clock for WM8762 supports audio sampling rates from 128fs to 768fs, where fs is

the audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The

master clock is used to operate the digital filters and the noise shaping circuits.

The WM8762 has a master clock detection circuit that automatically determines the relation

between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If

there is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output.

The master clock should be synchronised with LRCIN, although the WM8762 is tolerant of

phase differences or jitter on this clock.

MASTER CLOCK FREQUENCY (MHZ) (MCLK)

SAMPLING

RATE

(LRCIN)

128fs

192fs

256fs

384fs

512fs

768fs

32kHz

4.096

6.144

8.192

12.288

16.384

24.576

44.1kHz

5.6448

8.467

11.2896

16.9340

22.5792

33.8688

48kHz

6.114

9.216

12.288

18.432

24.576

36.864

96kHz

12.288

18.432

24.576

36.864

Unavailable

Unavailable

192kHz

24.576

36.864

Unavailable

Unavailable

Unavailable

Unavailable

Table 1 Master Clock Frequencies Versus Sampling Rate

LEFT CHANNEL

RIGHT CHANNEL

LRCIN

BCKIN

DIN

1/fs

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

LSB

MSB