Production Data

WM8766

w

PD Rev 4.1 July 2005

21

be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the

inverse of that shown in Figure 13, Figure 14, Figure 15, Figure 16, and Figure 17.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0000011

Interface Control

3

BCP

0

BCLK Polarity (DSP Modes):

0: Normal BCLK polarity

1: Inverted BCLK polarity

The IWL[1:0] bits are used to control the input word length.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0000011

Interface Control

5:4

IWL

[1:0]

00

Input Word Length:

00 : 16 bit data

01: 20 bit data

10: 24 bit data

11: 32 bit data

Note: 32-bit right justified mode is not supported.

In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the

DAC is programmed to receive 16 or 20 bit data, the WM8766 pads the unused LSBs with zeros. If

the DAC is programmed into 32 bit mode, the 8 LSBs are ignored.

Note: In 24 bit I

minimum of 24 BCLKs and low for a minimum of 24 BCLKs.

A number of options are available to control how data from the Digital Audio Interface is applied to

the DAC channels.