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WM8955BLGECO/RV 数据表(PDF) 12 Page - Wolfson Microelectronics plc |
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WM8955BLGECO/RV 数据表(HTML) 12 Page - Wolfson Microelectronics plc |
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12 / 44 page  WM8955BL Production Data w PD Rev 4.1 February 2007 12 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK t MCLKL t MCLKH t MCLKY Figure 1 System Clock Timing Requirements Test Conditions CLKDIV2 = 0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25 oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT System Clock Timing Information MCLK System clock pulse width high TMCLKL 21 ns MCLK System clock pulse width low TMCLKH 21 ns MCLK System clock cycle time TMCLKY 54 ns MCLK duty cycle TMCLKDS 60:40 40:60 Test Conditions CLKDIV2 = 1, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25 oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT System Clock Timing Information MCLK System clock pulse width high TMCLKL 10 ns MCLK System clock pulse width low TMCLKH 10 ns MCLK System clock cycle time TMCLKY 27 ns AUDIO INTERFACE TIMING – MASTER MODE BCLK (Output) DACLRC (Output) DACDAT t DST t DHT t DL Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface) Test Conditions DBVDD = 3.3V, DGND = 0V, TA = +25 oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Bit Clock Timing Information BCLK rise time (10pF load) tBCLKR 3 ns BCLK fall time (10pF load) tBCLKF 3 ns BCLK duty cycle (normal mode, BCLK = MCLK/n) tBCLKDS 50:50 BCLK duty cycle (USB mode, BCLK = MCLK) tBCLKDS TMCLKDS |
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