WM8955BLGECOSLASHRV datasheet(13/44 Pages) WOLFSON

13 / 44 page

Production Data

WM8955BL

PD Rev 4.1 February 2007

Test Conditions

DBVDD = 3.3V, DGND = 0V, TA = +25

oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

DACLRC propagation delay from BCLK falling

edge

tDL

DACDAT setup time to BCLK rising edge

tDST

DACDAT hold time from BCLK rising edge

tDHT

AUDIO INTERFACE TIMING – SLAVE MODE

BCLK

DACLRC

BCH

BCL

BCY

DACDAT

LRSU

LRH

Figure 3 Digital Audio Data Timing – Slave Mode (see Control Interface)

Test Conditions

DBVDD = 3.3V, DGND = 0V, TA = +25

oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

BCLK cycle time

tBCY

BCLK pulse width high

tBCH

BCLK pulse width low

tBCL

DACLRC setup time to BCLK rising edge

tLRSU

DACLRC hold time from BCLK rising edge

tLRH

DACDAT hold time from BCLK rising edge

tDH

CONTROL INTERFACE TIMING – 3-WIRE MODE

CSB

SCLK

SDIN

CSL

DHO

DSU

CSH

SCY

SCH

SCL

SCS

LSB

CSS

Figure 4 Control Interface Timing – 3-Wire Serial Control Mode

WM8955BLGECO/RV 数据表(PDF) 13 Page - Wolfson Microelectronics plc

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