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WM8976 数据表(PDF) 86 Page - Wolfson Microelectronics plc |
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WM8976 数据表(HTML) 86 Page - Wolfson Microelectronics plc |
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86 / 108 page  WM8976 Pre-Production w PP Rev 3.0 April 2006 86 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 0 DACMONO 0 Selects between stereo and mono DAC operation: 0=Stereo device operation 1=Mono device operation. DAC data appears in ‘left’ phase of LRC Digital Audio Interfaces 8:6 000 Reserved 5 WL8 0 Companding Control 8-bit mode 0=off 1=device operates in 8-bit mode Digital Audio Interfaces 4:3 DAC_COMP 00 DAC companding 00=off (linear mode) 01=reserved 10=µ-law 11=A-law Digital Audio Interfaces 2:1 ADC_COMP 00 ADC companding 00=off (linear mode) 01=reserved 10=µ-law 11=A-law Digital Audio Interfaces 5 (05h) 0 LOOPBACK 0 Digital loopback function 0=No loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input. Digital Audio Interfaces 8 CLKSEL 1 Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output Digital Audio Interfaces 7:5 MCLKDIV 010 Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 Digital Audio Interfaces 4:2 BCLKDIV 000 Configures the BCLK output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=MCLK) 001=divide by 2 (BCLK=MCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved Digital Audio Interfaces 1 0 Reserved 6 (06h) 0 MS 0 Sets the chip to be master over LRC and BCLK 0=BCLK and LRC clock are inputs 1=BCLK and LRC clock are outputs generated by the WM8976 (MASTER) Digital Audio Interfaces |
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