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WM9713LGEFL/V 数据表(PDF) 85 Page - Wolfson Microelectronics plc |
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WM9713LGEFL/V 数据表(HTML) 85 Page - Wolfson Microelectronics plc |
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85 / 108 page  Pre-Production WM9713L w PP Rev 3.0 June 2006 85 REGISTER MAP R e g N a m e 15 14 13 12 11 10 9 8 765432 1 0 D e f a ult Reset 0 SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 6174h Speaker Volume M UL ZCL M UR ZCR 8080h Headphone V olume M UL ZCL M UR ZCR 8080h OUT3/ 4 Vo lume M U4 ZC4 M U3 ZC3 8080h M ONO V ol & M ONOIN PGA Vol / Routing M 2H M 2S 0 M U ZC C880h LINEIN PGA Volume / Rout ing L2H L2S L2M 0 0 0 E808h DAC PGA Volume / Rout ing D2H D2S D2M 0 0 0 E808h M IC PGA V olume 0 0 0 0 0 0 0808h M IC Rout ing 000000 00 M A2M M B 2M M IC2M BST 00DAh Reco rd PGA Volume RM U GRL ZC GRR 8000h Reco rd Rout ing / M ux Select R2M BST 0REC BST D600h PCBEEP Volume / Rout ing B2H B2S B 2M 0 0 0 0 A AA0h VxDAC Volume / Rout ing V2H V2S V 2M 0 0 0 0 A AA0h AUXDAC V olume / Routing A2H A2S A 2M 0 0 0 0 A AA0h Output PGA M ux Select 0000h DAC 3D Control & INV M ux Select 0000 3DLC 3DUC 0000h DAC Tone Cont rol BB 0 0 B C 0 DAT 0 TC 0F0Fh M IC Input Select & Bias / Det ect Ctrl MB OP 2EN MBOP1 EN MB VO L 0040h Output Volume M apping (Jack Insert ) 000000 00000 JIEN 0000h Powerdown Ct rl/ Stat 0 PR6 PR5 PR4 PR3 PR2 PR1 PR0 0000 REF ANL DA C ADC 7F00h Ext ended Audio ID ID1 ID0 0 0 REV1 REV0 A M A P LDAC SDAC CDA C 0 0 VRM SPDIF DRA VRA 0405h Ext 'd Audio St at / Ct rl 00000 SPCV 0000 0 SEN 0 VRA 0410h Audio DACs Sample Rate B B80h AUXDAC Sample Rat e B B80h Audio ADCs Sample Rate B B80h PCM codec control CTRL 0 VDAC OSR CP FSP 4523h SPDIF cont rol V DRS L PRE COPY AUD IB PRO 2000h Powerdown (1) PA DCP D VM ID 1M TSHUT VX DA C AUXD AC VREF PLL 1 DACL DACR ADCL ADCR HPLX HPRX SPKX M X FDFFh Powerdown (2) M CD M IC BIAS M ONO OUT4 OUT3 HPL HPR SPKL SPKR LL LR M OIN M A M B M PA M PB FFFFh General Purpose 0 0 3DE 000 00 LB 00000 00 0000h Fast Power-Up Control 000000 000 M ONO SPKL SPKR HPL HPR OUT3 OUT4 0000h M CLK / PLL Cont rol 0 CLKSR C 0 CLKBX 2 CLKA X 2 CLKM U X 0080h M CLK / PLL Cont rol LF SDM DIVSEL DIVCTL 0 0000h GPIO Pin Configurat ion 11111 11 GC8 GC7 GC6 GC5 GC4 GC3 GC2 GC1 0 FFFEh GPIO Pin Polarit y / Type C1P C2P PP AP TP SP M P GP8 GP7 GP6 GP5 GP4 GP3 GP2 GP1 1 FFFFh GPIO Pin Sticky C1S C2S PS AS TS SS M S GS8 GS7 GS6 GS5 GS4 GS3 GS2 GS1 0 0000h GPIO Pin Wake-Up C1W C2W PW AW TW SW M W GW8 GW7 GW6 GW5 GW4 GW3 GW2 GW1 0 0000h GPIO Pin Stat us C1I C2I PI AI TI SI M I GI8 GI7 GI6 GI5 GI4 GI3 GI2 GI1 0 GPIO pins GPIO Pin Sharing 11111 11 GE8 GE7 GE6 GE5 GE4 GE3 GE2 1 0 FFFEh GPIO Pull UP/ DOWN Ct rl PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 4000h Addit ional Funct ions (1) 0 0 0 0 RSTDIS WAKEE N IRQ INV 0000h Addit ional Funct ions (2) AMUTE C1REF C2 REF 0 AM EN ADCO HPF 0 0000h ALC Cont rol B032h ALC / Noise Gate Cont rol 0 NGA T 0 NGG 3E00h AUXDAC input cont rol XSLE 0000h Digitiser Reg 1 000000 POLL CTC COO 0000h Digitiser Reg 2 000000 SLEN 0006h Digitiser Reg 3 RPR 45W PDEN PDPOL WAIT PIL 0001h Digitiser Read Back PNDN 0000h Vend or ID1 574Dh Vend or ID2 4C13h PENDIV DCDRVSEL EARSPKSEL M ODE DIV SEL WL FM T SPSR CC (Cat egory Code) 7Eh ASCII charact er “ L” Device Identifier AUXDA CSLT AUXDA C VA L ADCSEL 7A h ADCSRC A DCD (TOUCHPA NEL ADC Y DA TA) 7Ch A SCII charact er “ W” A SCII charact er “ M ” DEL SLT 78h PRP M SK RPU 74h 76h CR 64h ASS 60h 6 2h ALCSEL M AX GAIN ZCTIM EOUT NGTH (threshold) ALCL (t arget level) HLD (hold t ime) 5Ch C1SRC C2SRC V BIA S 58h 5A h COM P2DEL Die Revision HPM ODE JSEL 50h 52h 54h 56h 4Ch 4Eh 40h 42h 44h 46h 3Ch 3Eh 36h 3Ah 2Eh AUXDACSR (Auxiliary DAC Sample Rate) 32h ADCSR (Audio ADCs Sample Rat e) 2Ah SPSA 2Ch DA CSR (Audio DA Cs Sample Rat e) 24h 26h DCY (decay time) ATK (at tack t ime) N[3:0] PGADDR PGDA TA SEXT[6 :4] SEXT[3:0] 28h 20h BA SS TRBL 2 2h M ICCM PSEL M PA SEL M PA BST M PBBST M CDTHR M CDSCTHR 1Eh INVA INV B 3DDEPTH HPL HPR OUT3 OUT4 1Ch M ONO SPKL SPKR 1A h A2HV OL A2SVOL A2M VOL 18h V2HV OL V2SVOL V2M VOL RECSL RECSR 16h B2HV OL B2SVOL B2M VOL 14h R2H R2 HVOL R2M 10h MIC2H M IC2HVOL 12h (Ext ended) RECVOLL (Ext ended ) RECVOLR 0Ch DACLV OL DACRVOL 0Eh MICAV OL M ICBV OL 08h M ONOINVOL M ONOV OL 0Ah LINELV OL LINERVOL 06h OUT4VOL OUT3VOL 04h HPLVOL HPRV OL 00h 02h SPKLVOL SPKRVOL Table 68 WM9713L Register Map Note: Register 46h provides access to a sub-page address system to set the SPLL[6:0] and K[21:0] register bits (see Table 6). |
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