AD8224ACPZ-R7 datasheet(20/28 Pages) AD

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AD8224

Rev. 0 | Page 20 of 28

Table 11. Gains Achieved Using 1% Resistors

1% Standard Table Value of RG (Ω)

Calculated Gain

49.9 k

1.990

12.4 k

4.984

5.49 k

9.998

2.61 k

19.93

1.00 k

50.40

499

100.0

249

199.4

100

495.0

49.9

991.0

The AD8224 defaults to G = 1 when no gain resistor is used.

The tolerance and gain drift of the RG resistor should be added

to the AD8224 specifications to determine the total gain

accuracy of the system. When the gain resistor is not used,

gain error and gain drift are kept to a minimum.

REFERENCE TERMINAL

The output voltage of the AD8224 is developed with respect to

the potential on the reference terminal. This is useful when the

output signal needs to be offset to a precise midsupply level. For

example, a voltage source can be tied to the REF1 or REF2 pin

to level-shift the output so that the AD8224 can drive a single-

supply ADC. Pin REFx is protected with ESD diodes and

should not exceed either +VS or −VS by more than 0.5 V.

For best performance, source impedance to the REF terminal

should be kept below 1 Ω. As shown in Figure 52 the reference

terminal, REF, is at one end of a 20 kΩ resistor. Additional

impedance at the REF terminal adds to this 20 kΩ resistor and

results in amplification of the signal connected to the positive

input. The amplification from the additional RREF can be

computed by

(

)

REF

kΩ

Only the positive signal path is amplified; the negative path is

unaffected. This uneven amplification degrades the amplifier’s

CMRR.

INCORRECT

AD8224

VREF

CORRECT

AD8224

OP2177

–

VREF

CORRECT

AD8224

–

VREF

Figure 53. Driving the Reference Pin

LAYOUT

The AD8224 is a high precision device. To ensure optimum

performance at the PC board level, care must be taken in the

design of the board layout. The AD8224 pinout is arranged in

a logical manner to aid in this task.

Package Considerations

The AD8224 is available in a 16-lead, 4 mm × 4 mm LFCSP.

Blindly copying the footprint from another 4 mm × 4 mm

LFCSP part is not recommended; it may not have the same

thermal pad size and leads. Refer to the Outline Dimensions

section to verify that the PCB symbol has the correct dimensions.

Space between the leads and thermal pad should be kept as

wide as possible for the best bias current performance. To

maintain the AD8224 ultralow bias current performance, the

thermal pad area can be reduced to extend the gap between the

leads and the pad.

Thermal Pad

The AD8224 4 mm × 4 mm LFCSP comes with a thermal pad.

This pad is connected internally to +VS. The pad can either be

left unconnected or connected to the positive supply rail.

To preserve maximum pin compatibility with other dual

instrumentation amplifiers, such as the AD8222, leave the pad

unconnected. This can be done by not soldering the paddle at

all or by soldering the part to a landing that is a not connected

to any other net. For high vibration applications, a landing is

recommended.

Because the AD8224 dissipates little power, heat dissipation is

rarely an issue. If improved heat dissipation is desired (for example,

when driving heavy loads), connect the thermal pad to the

positive supply rail. For the best heat dissipation performance,

the positive supply rail should be a plane in the board. See

the Thermal Resistance section for more information.

Common-Mode Rejection over Frequency

The AD8224 has a higher CMRR over frequency than typical

in-amps, which gives it greater immunity to disturbances, such

as line noise and its associated harmonics. A well-implemented

layout is required to maintain this high performance. Input

source impedances should be matched closely. Source resistance

should be placed close to the inputs so that it interacts with as

little parasitic capacitance as possible.

Parasitics at the RGx pins can also affect CMRR over frequency.

The PCB should be laid out so that the parasitic capacitances at

each pin match. Traces from the gain setting resistor to the RGx

pins should be kept short to minimize parasitic inductance.

Reference

Errors introduced at the reference terminal feed directly to

the output. Take care to tie the REFx pins to the appropriate

local ground.

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