AD8331ARQZ-R7 datasheet(31/40 Pages) AD

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AD8331/AD8332/AD8334

Rev. E | Page 31 of 40

Parallel connected devices can be driven by a common voltage

source or DAC. Decoupling should take into account any

bandwidth considerations of the drive waveform, using the total

distributed capacitance.

If gain control noise in LO gain mode becomes a factor,

maintaining ≤15 nV/√Hz noise at the GAIN pin ensures

satisfactory noise performance. Internal noise prevails below

15 nV/√Hz at the GAIN pin. Gain control noise is negligible in

HI gain mode.

VCM Input

The common-mode voltage of Pin VCM, Pin VOL, and Pin VOH

defaults to 2.5 V dc. With output ac-coupled applications, the

VCM pin is unterminated; however, it must still be bypassed in

close proximity for ac grounding of internal circuitry. The VGA

outputs can be dc connected to a differential load, such as an

ADC. Common-mode output voltage levels between 1.5 V and

3.5 V can be realized at Pin VOH and Pin VOL by applying the

desired voltage at Pin VCM. DC-coupled operation is not

recommended when driving loads on a separate PC board.

The voltage on the VCM pin is sourced by an internal buffer

with an output impedance of 30 Ω and a ±2 mA default output

current (see Figure 83). If the VCM pin is driven from an

external source, its output impedance should be <<30 Ω and its

current drive capability should be >>2 mA. If the VCM pins of

several devices are connected in parallel, the external buffer

should be capable of overcoming their collective output currents.

When a common-mode voltage other than 2.5 V is used, a

voltage-limiting resistor, RCLMP, is needed to protect against

overload.

VCM

NEW VCM

RO << 30Ω

100pF

2mA MAX

30Ω

0.1µF

INTERNAL

CIRCUITRY

AC GROUNDING FOR

INTERNAL CIRCUITRY

Figure 83. VCM Interface

Logic Inputs—ENB, MODE, and HILO

The input impedance of all enable pins is nominally 25 kΩ and

can be pulled up to 5 V (a pull-up resistor is recommended) or

driven by any 3 V or 5 V logic families. The enable pin, ENB,

powers down the VGA—when pulled low, the VGA output

voltages are near ground. Multiple devices can be driven from a

common source. Consult Table 3, Table 4, Table 5, and Table 6

for circuit functions controlled by the enable pins.

Pin HILO is compatible with 3 V or 5 V CMOS logic families. It

is either connected to ground or pulled up to 5 V, depending on

the desired gain range and output noise.

Optional Output Voltage Limiting

The RCLMP pin provides the user with a means to limit the

output voltage swing when used with loads that have no

provisions for prevention of input overdrive. The peak-to-peak

limited voltage is adjusted by a resistor to ground, and Table 8

lists several voltage levels and the corresponding resistor value.

Unconnected, the default limiting level is 4.5 V p-p.

Note that third harmonic distortion increases as waveform

amplitudes approach clipping. For lowest distortion, the clamp

level should be set higher than the converter input span. A

clamp level of 1.5 V p-p is recommended for a 1 V p-p linear

output range, 2.7 V p-p for a 2 V p-p range, or 1 V p-p for

a 0.5 V p-p operation. The best solution is determined

experimentally. Figure 84 shows third harmonic distortion

as a function of the limiting level for a 2 V p-p output signal.

A wider limiting level is desirable in HI gain mode.

–20

–30

–40

–50

–60

–70

–80

1.5

2.0

2.5

3.0

4.0

3.5

4.5

5.0

CLAMP LIMIT LEVEL (V p-p)

VGAIN = 0.75V

HILO = LO

HILO = HI

Figure 84. HD3 vs. Clamping Level for 2 V p-p Differential Input

Table 8. Clamp Resistor Values

Clamp Resistor Value (kΩ)

Clamp Level (V p-p)

HILO = LO

HILO = HI

0.5

1.21

1.0

2.74

2.21

1.5

4.75

4.02

2.0

7.5

6.49

2.5

9.53

3.0

16.9

14.7

3.5

26.7

23.2

4.0

49.9

39.2

4.4

100

73.2

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