LP87702 datasheet(42/99 Pages) TI

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8.5 Programming

8.5.1 I2C-Compatible Interface

The I2C-compatible synchronous serial interface provides access to the programmable functions and registers

on the device. This protocol uses a two-wire interface for bidirectional communications between the ICs

connected to the bus. The two interface lines are the serial data line (SDA) and the serial clock line (SCL).

Every device on the bus is assigned a unique address and acts as either a master or a slave depending on

whether it generates or receives the serial clock SCL. The SCL and SDA lines should each have a pull-up

resistor placed somewhere on the line and remain HIGH even when the bus is idle. The LP87702-Q1 supports

standard mode (100 kHz), fast mode (400 kHz), fast mode plus (1 MHz), and high-speed mode (3.4 MHz).

8.5.1.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the

state of the data line can only be changed when clock signal is LOW.

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

SCL

SDA

Figure 8-15. Data Validity Diagram

8.5.1.2 Start and Stop Conditions

The LP87702-Q1 is controlled through an I2C-compatible interface. START and STOP conditions classify the

beginning and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW while

SCL is HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The I2C

master always generates the START and STOP conditions.

SDA

START

Condition

SCL

STOP

Condition

Figure 8-16. Start and Stop Sequences

The I2C bus is considered busy after a START condition and free after a STOP condition. The I2C master can

generate repeated START conditions during data transmission. A START and a repeated START condition are

equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock signal (SCL). In

other words, the state of SDA can only be changed when SCL is LOW. Figure 8-17 shows the SDA and SCL

signal timing for the I2C-Compatible Bus. See Section 7.6 for timing values.

LP87702-Q1

SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021

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