LP87702 datasheet(21/99 Pages) TI

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Table 8-2. PLL Operation

DEVICE

OPERATION MODE

EN_PLL

PLL AND CLOCK

DETECTOR STATE

INTERRUPT FOR

EXTERNAL CLOCK

CLOCK

STANDBY

Disabled

Internal RC

ACTIVE

Disabled

Internal RC

STANDBY

Enabled

When external clock

disappears or appears

Automatic change to internal

RC oscillator when External

clock is not available

ACTIVE

Enabled

When external clock

disappears or appears

Automatic change to internal

RC oscillator when External

clock is not available

8.3.5 Power-Up

The power-up sequence for the LP87702-Q1 is as follows:

• VANA (and VIN_Bx) reach minimum recommended levels (VVANA > VANAUVLO).

• Driving the NRST input high initiates OTP read and enables the system I/O interface. Minimum delay from

the NRST reset input rising edge to I2C write or read access is 1.2 ms.

• Device enters STANDBY mode. Watchdog operation starts.

• The host can change the default register setting by I2C if needed.

• The converters can be enabled or disabled and the GPOx signals can be controlled by ENx pins and by I2C

interface.

8.3.6 Buck and Boost Control

8.3.6.1 Enabling and Disabling Converters

The buck converters can be enabled when the device is in STANDBY or ACTIVE state. There are two ways to

enable and disable the buck converters:

• Using BUCKx_EN bit in BUCKx_CTRL_1 register (BUCKx_EN_PIN_CTRL bit is 00 in BUCKx_CTRL_1

• Using ENx control pin (BUCKx_EN bit is 1 in BUCKx_CTRL_1 register and BUCKx_EN_PIN_CTRL bit is not

00 in BUCKx_CTRL_1 register)

Similarly there are two ways to enable and disable the boost converter:

• Using BOOST_EN bit in BOOST_CTRL register (BOOST_EN_PIN_CTRL bit is 0 in BOOST_CTRL register)

• Using ENx control pin (BOOST_EN bit is 1 in BOOST_CTRL register and BOOST_EN_PIN_CTRL bit is not

00 in BOOST_CTRL register)

If the ENx control pin is used to enable and disable, then the delay from the control signal rising edge to start-up

is set by BUCKx_STARTUP_DELAY[3:0] bits in BUCKx_DELAY register and BOOST_STARTUP_DELAY[3:0]

bits in BOOST_DELAY register. The delay from falling edge of control signal to shutdown is set by

BUCKx_SHUTDOWN_DELAY[3:0] bits in BUCKx_DELAY register and BOOST_SHUTDOWN_DELAY[3:0] bits

in BOOST_DELAY register. The delays are valid only when ENx pin control is used, not when converters are

enabled by I2C write to BUCKx_EN and BOOST_EN bits.

The control of the converters (with 0-ms delays) is shown in Table 8-3.

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LP87702-Q1

SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021

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