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AT43USB326 数据表(PDF) 21 Page - ATMEL Corporation |
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AT43USB326 数据表(HTML) 21 Page - ATMEL Corporation |
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21 / 102 page ![]() 21 AT43USB326 3313D–USB–04/06 When the USB hardware is reset, the compound device is de-configured and has to be re- enumerated by the host. When the microcontroller is reset, all I/O registers are then set to their initial values, and the program starts execution from address $000. The instruction placed in address $000 must be a JMP instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 6 shows the reset logic. The user can select the start-up time according to typical oscillator start-up. The number of WDT oscilla- tor cycles used for each time-out is shown in Table 7. Figure 6. Reset Logic Power-on Reset A Power-on Reset (POR) circuit ensures that the device is reset from power-on. An internal timer clocked from the Watchdog timer oscillator prevents the MCU from starting until after a certain period after V CC has reached the power-on threshold voltage, regardless of the VCC rise time. If the build-in start-up delay is sufficient, RESET can be connected to V CC directly or via an external pull-up resistor. By holding the pin low for a period after V CC has been applied, the Power-on Reset period can be extended. FSTRT Cntr Reset USB Reset OR POR Ckt Reset Ckt Watchdog Timer Divider 14-bit Cntr VCC RSTN System Clock S R ON Table 7. Number of Watchdog Oscillator Cycles FSTRT Time-out at V CC = 5V Number of WDT cycles Programmed 1.1 ms 1K Unprogrammed 16.0 ms 16K |
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