AT43USB326 datasheet(39/102 Pages) ATMEL

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AT43USB326

3313D–USB–04/06

Watchdog Timer

The Watchdog Timer is clocked from a 1 MHz clock derived from the 6 MHz on chip oscillator.

By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted,

see Table 11 for a detailed description. The WDR (Watchdog Reset) instruction resets the

Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset

period. If the reset period expires without another Watchdog reset, the AT43USB326 resets

and executes from the reset vector.

To prevent unintentional disabling of the watchdog, a special turn-off sequence must be fol-

lowed when the watchdog is disabled. Refer to the description of the Watchdog Timer Control

Figure 11. Watchdog Timer

Watch Dog Timer Control Register – WDTCR

• Bits 7..5 – Res: Reserved Bits

These bits are reserved bits in the AT43USB326 and will always read as zero.

•Bit 4 – WDTOE: Watch Dog Turn-Off Enable

This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be

disabled. Once set, the hardware will clear this bit to zero after four clock cycles. Refer to the

description of the WDE bit for a watchdog disable procedure.

•Bit 3 – WDE: Watch Dog Enable

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero)

the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set

(one). To disable an enabled watchdog timer, the following procedure must be followed:

Bit

$21 ($41)

–

WDTOE

WDE

WDP2

WDP1

WDP0

WDTCR

Read/Write

R/W

Initial Value

1 MHz Clock

MCU Reset

WDE

WDP2

WDP1

WDP0

Watchdog

Reset

Watchdog Prescaler

AT43USB326 数据表(PDF) 39 Page - ATMEL Corporation

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