AT89LP214 datasheet(80/90 Pages) ATMEL

80 / 90 page

3538A–MICRO–7/06

AT89LP213/214 [Preliminary]

Figure 24-6. Shift Register Mode Timing Waveform

24.6

Test Conditions

24.6.1

AC Testing Input/Output Waveform(1)

Note:

1. AC Inputs during testing are driven at V

CC - 0.5V for a logic “1” and 0.45V for a logic “0”. Timing measurements are made at

VIH min. for a logic “1” and VIL max. for a logic “0”.

24.6.2

Float Waveform(1)

Note:

1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to

float when 100 mV change from the loaded VOH/VOL level occurs.

24.5

Serial Port Timing: Shift Register Mode Test Conditions

The values in this table are valid for V

CC = 2.4V to 5.5V and Load Capacitance = 80 pF.

Symbol

Parameter

Variable Oscillator

Units

Min

Max

tXLXL

Serial Port Clock Cycle Time

2tCLCL -15

µs

QVXH

Output Data Setup to Clock Rising Edge

CLCL -15

tXHQX

Output Data Hold after Clock Rising Edge

tCLCL -15

tXHDX

Input Data Hold after Clock Rising Edge

XHDV

Input Data Valid to Clock Rising Edge

VALID

CLOCK

WRITE TO SBUF

OUTPUT DATA

CLEAR RI

INPUT DATA

AT89LP214 数据表(PDF) 80 Page - ATMEL Corporation

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