AT89LP214 datasheet(56/90 Pages) ATMEL

56 / 90 page

3538A–MICRO–7/06

AT89LP213/214 [Preliminary]

Note:

1. Debouncing modes require the use of Timer 1 to generate the sampling delay.

Table 19-1.

ACSR

– Analog Comparator Control & Status Register

ACSR = 97H

Reset Value = XXX0 0000B

Not Bit Addressable

––

CIDL

CEN

CM3

CM1

CM0

Bit

543

Symbol

Function

CIDL

Comparator Idle Enable. If CIDL = 1 the comparator will continue to operate during Idle mode. If CIDL = 0 the

comparator is powered down during Idle mode. The comparator is always shut down during Power-down mode.

Comparator Interrupt Flag. Set when the comparator output meets the conditions specified by the CM [2:0] bits and CEN

is set. The flag must be cleared by software. The interrupt may be enabled/disabled by setting/clearing bit 6 of IE.

CEN

Comparator Enable. Set this bit to enable the comparator. Clearing this bit will force the comparator output low and

prevent further events from setting CF. When CEN = 1 the analog input pins, P1.0 and P1.1, have their digital inputs

disabled.

CM [2:0]

Comparator Interrupt Mode

CM2

CM1

CM0

Interrupt Mode

000Negative (Low) level

001Positive edge

010Toggle with debouncing(1)

011Positive edge with debouncing(1)

100Negative edge

101Toggle

110Negative edge with debouncing(1)

111Positive (High) level

AT89LP214 数据表(PDF) 56 Page - ATMEL Corporation

AT89LP214 数据表(HTML) 56 Page - ATMEL Corporation

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