AT89LP216-20PI datasheet(14/90 Pages) ATMEL

14 / 90 page

3621A–MICRO–6/06

AT89LP216 [Preliminary]

10.2

Brown-out Reset

The AT89LP216 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V

CC level

during operation by comparing it to a fixed trigger level. The trigger level for the BOD is nomi-

nally 2.2V. The purpose of the BOD is to ensure that if V

CC fails or dips while executing at speed,

the system will gracefully enter reset without the possibility of errors induced by incorrect execu-

tion. A BOD sequence is shown in Figure 10-3. When V

CC decreases to a value below the

trigger level V

BOD, the internal reset is immediately activated. When VCC increases above the

trigger level, the start-up timer releases the internal reset after the specified time-out period has

expired (Table 10-1). The Brown-out Detector must be enabled by setting the BOD Enable Fuse.

(See “User Configuration Fuses” on page 71.).

Figure 10-3. Brown-out Detector Reset

10.3

External Reset

The P1.3/RST pin can function as either an active-LOW reset input or as a digital general-

purpose I/O, P1.3. The Reset Pin Enable Fuse, when set to “1”, enables the external reset input

function on P1.3. (See “User Configuration Fuses” on page 71.). When cleared, P1.3 may be

used as an input or output pin. When configured as a reset input, the pin must be held low for at

least two clock cycles to trigger the internal reset.

Note:

During a power-up sequence, the fuse selection is always overridden and therefore the pin will

always function as a reset input. An external circuit connected to this pin should not hold this

pin LOW during a power-on sequence as this will keep the device in reset until the pin tran-

sitions high. After the power-up delay, this input will function either as an external reset input or

as a digital input as defined by the fuse bit. Only a power-up reset will temporarily override the

selection defined by the reset fuse bit. Other sources of reset will not override the reset fuse bit.

P1.3/RST also serves as the In-System Programming (ISP) enable. ISP is enabled when the

external reset pin is held low. When the reset pin is disabled by the fuse, ISP may only be entered

by pulling P1.3 low during power-up.

Table 10-1.

Start-up Timer Settings

SUT Fuse 1

SUT Fuse 0

Clock Source

SUT (± 5%) µs

Internal RC/External Clock

Crystal Oscillator

1024

Internal RC/External Clock

512

Crystal Oscillator

2048

Internal RC/External Clock

1024

Crystal Oscillator

4096

Internal RC/External Clock

4096

Crystal Oscillator

16384

VCC

Time-out

VPOR

Internal

Reset

tSUT

VBOD

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