AT89LP216-20PI datasheet(52/90 Pages) ATMEL

52 / 90 page

3621A–MICRO–6/06

AT89LP216 [Preliminary]

Table 18-3.

SPSR – SPI Status Register

SPSR Address = E8H

Reset Value = 000X X000B

Not Bit Addressable

SPIF

WCOL

LDEN

–

SSIG

DISSO

ENH

Bit

76543

210

Symbol

Function

SPIF

SP interrupt flag. When a serial transfer is complete, the SPIF bit is set and an interrupt is generated if SPIE = 1 and

ES = 1. The SPIF bit is cleared by reading the SPI status register followed by reading/writing the SPI data register.

WCOL

When ENH = 0: Write collision flag. The WCOL bit is set if the SPI data register is written during a data transfer. During

data transfer, the result of reading the SPDR register may be incorrect, and writing to it has no effect. The WCOL bit

(and the SPIF bit) are cleared by reading the SPI status register followed by reading/writing the SPI data register.

When ENH = 1: WCOL works in Enhanced mode as Tx Buffer Full. Writing during WCOL = 1 in enhanced mode will

overwrite the waiting data already present in the Tx Buffer. In this mode, WCOL is no longer reset by the SPIF reset but

is reset when the write buffer has been unloaded into the serial shift register.

LDEN

Load enable for the Tx buffer in enhanced SPI mode.

When ENH is set, it is safe to load the Tx Buffer while LDEN = 1 and WCOL = 0. LDEN is high during bits 0 - 3 and is low

during bits 4 - 7 of the SPI serial byte transmission time frame.

SSIG

Slave Select Ignore. If SSIG = 0, the SPI will only operate in slave mode if SS (P1.4) is pulled low. When SSIG = 1, the

SPI ignores SS in slave mode and is active whenever SPE (SPCR.6) is set. P1.4 may be used as a regular I/O pin when

SSIG = 1.

DISSO

Disable slave output bit.

When set, this bit causes the MISO pin to be tri-stated so more than one slave device can share the same interface with

a single master. Normally, the first byte in a transmission could be the slave address and only the selected slave should

clear its DISSO bit.

ENH

Enhanced SPI mode select bit. When ENH = 0, SPI is in normal mode, i.e. without write double buffering.

When ENH = 1, SPI is in enhanced mode with write double buffering. The Tx buffer shares the same address with the

SPDR register.

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