AM263P4 datasheet(84/154 Pages) TI

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6.11.2 Power Supply Sequencing

This section describes power supply sequencing required to ensure proper device operation.

6.11.2.1 Power-On and Reset Sequencing

AM263Px attempts to simplify the power reset requirements from previous Sitara MCU devices. There is no

sequencing requirement with respect to the primary core digital VDD 1.2-V and I/O power 3.3-V rails. There are

two on-die LDO that are supplied through the VDDS33 and VDDA33 power nets respectively. These on-die LDO

generate the required VDDS1V8 and VDDA1V8 1.8-V digital and analog power. The AM263Px does require the

minimum ramp time be respected for 3.3-V power-on. Additional PORz and SOP boot mode latch timing must be

respected by the EVM design as well. Figure 6-2 describes the device power-on sequencing.

Table 6-2. AM263Px Power-On Sequencing

PARAMETER

MIN

MAX

UNIT

tStartup

Time for 1.2-V and 3.3-V DC-DC converters to startup after being enabled. This is an

arbitrary amount of time - no constraint imposed by the device.

–

tPGood

Time for Power Good signals to be generated from DC-DC converters after rails are

stable. This is an arbitrary amount of time - no constraint imposed by the device.

–

tRamp_3V3

Ramp time of the VDDS3V3 and VDDA3V3 supplies. This is a requirement imposed by

the device.

0.1

–

tSOP_Sampled

Time from PORz de-assertion until the SOP[3:0] pins are sampled. This is a device

internal pentameter. Sampling happens when the internally generated supplies are

stable. For information only. Refer to TSU_SOP and TH_SOP parameters for application

usage.

–

tSU_SOP

Setup time for SOP relative to PORz assertion.

–

μs

tH_SOP

Hold time for SOP relative to WARMRSTn deassertion.

–

μs

tWARMRSTn

Time from PORz de-assertion until the device de-asserts the WARMRESETn signal.

2.0

–

TI Information - Selective Disclosure

AM263P4, AM263P2, AM263P1, AM263P4-Q1, AM263P2-Q1, AM263P1-Q1

SPRSP81 – OCTOBER 2023

www.ti.com

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