SC1933C datasheet(6/28 Pages) POWERINT

6 / 28 page

Rev. C 11/18

SC1933C/SC1936C

www.power.com

The most likely event that could require an additional handshake is

when the primary stops switching as the result of a momentary line

brown-out event. When the primary resumes operation, it will default

to a start-up condition and attempt to detect handshake pulses from

the secondary.

If the secondary does not detect that the primary responds to switching

requests for 8 consecutive cycles, or if the secondary detects that the

primary is switching without cycle requests for 4 or more consecutive

cycles, the secondary controller will initiate a second handshake

sequence. This provides additional protection against cross-conduction

of the SR FET while the primary is switching. This protection mode

also prevents an output overvoltage condition in the event that the

primary is reset while the secondary is still in control.

Wait and Listen

When the primary resumes switching after initial power-up recovery

from an input line voltage fault (UV or OV) or an auto-restart event, it

will assume control and require a successful handshake to relinquish

control to the secondary controller.

As an additional safety measure the primary will pause for an

auto-restart on-time period, t

AR (~82 ms), before switching. During

this “wait” time, the primary will “listen” for secondary requests. If it

sees two consecutive secondary requests, separated by ~30 ms, the

primary will infer secondary control and begin switching in slave

mode. If no pulses occurs during the t

AR “wait” period, the primary

will begin switching under primary control until handshake pulses are

received.

Audible Noise Reduction Engine

The SC1933C/SC1936C features an active audible noise reduction

mode whereby the controller (via a “frequency skipping” mode of

operation) avoids the resonant band (where the mechanical structure

of the power supply is most likely to resonate − increasing noise

amplitude) between 7 kHz and 12 kHz - 143 ms and 83 ms. If a

secondary controller switch request occurs within this time window

from the last conduction cycle, the gate drive to the power switch is

inhibited.

Secondary Controller

As shown in the block diagram in Figure 5, the IC is powered by a

4.4 V (V

BPS) regulator which is supplied by either VOUT or FWD. The

SECONDARY BYPASS pin is connected to an external decoupling

capacitor and fed internally from the regulator block.

The FORWARD pin also connects to the negative edge detection

block used for both handshaking and timing to turn on the SR FET

connected to the SYNCHRONOUS RECTIFIER DRIVE pin. The

FORWARD pin voltage is used to determine when to turn off the

SR FET in discontinuous conduction mode operation. This is when

the voltage across the R

DS(ON) of the SR FET drops below zero volts.

In continuous conduction mode (CCM) the SR FET is turned off when

the feedback pulse is sent to the primary to demand the next

switching cycle, providing excellent synchronous operation, free of

any overlap for the FET turn-off.

The mid-point of an external resistor divider network between the

OUTPUT VOLTAGE and SECONDARY GROUND pins is tied to the

FEEDBACK pin to regulate the output voltage. The internal voltage

comparator reference voltage is V

FB (1.265 V).

The external current sense resistor connected between ISENSE and

SECONDARY GROUND pins is used to regulate the output current in

constant current regulation mode.

Minimum Off-Time

The secondary controller initiates a cycle request using the inductive-

connection to the primary. The maximum frequency of secondary-

cycle requests is limited by a minimum cycle off-time of t

OFF(MIN). This

is in order to ensure that there is sufficient reset time after primary

conduction to deliver energy to the load.

Maximum Switching Frequency

The maximum switch-request frequency of the secondary controller

is f

SREQ.

Frequency Soft-Start

At start-up the primary controller is limited to a maximum switching

frequency of f

SW and 75% of the maximum programmed current limit

at the switch-request frequency of 100 kHz.

The secondary controller temporarily inhibits the FEEDBACK short

protection threshold (V

FB(OFF)) until the end of the soft-start (tSS(RAMP))

time. After hand-shake is completed the secondary controller linearly

ramps up the switching frequency from f

SW to fSREQ over the tSS(RAMP)

time period.

In the event of a short-circuit or overload at start-up, the device will

move directly into CC (constant-current) mode. The device will go

into auto-restart (AR), if the output voltage does not rise above the

FB(AR) threshold before the expiration of the VOUT AR threshold timer

FB(AR)) after handshake has occurred.

The secondary controller enables the FEEDBACK pin-short protection

mode (V

FB(OFF)) at the end of the tSS(RAMP) time period. If the output

short maintains the FEEDBACK pin below the short-circuit threshold,

the secondary will stop requesting pulses triggering an auto-restart

cycle.

If the output voltage reaches regulation within the t

SS(RAMP) time

period, the frequency ramp is immediately aborted and the secondary

controller is permitted to go full frequency. This will allow the

controller to maintain regulation in the event of a sudden transient

loading soon after regulation is achieved. The frequency ramp will

only be aborted if quasi-resonant-detection programming has already

occurred.

Maximum Secondary Inhibit Period

Secondary requests to initiate primary switching are inhibited to

maintain operation below maximum frequency and ensure minimum

off-time. Besides these constraints, secondary-cycle requests are

also inhibited during the “ON” time cycle of the primary switch (time

between the cycle request and detection of FORWARD pin falling

edge). The maximum time-out in the event that a FORWARD pin

falling edge is not detected after a cycle requested is ~30 ms.

Output Overvoltage Protection

In the event that the sensed voltage on the FEEDBACK pin is 2%

higher than the regulation threshold, a bleed current of ~2.5 mA (3

mA max) is applied on the OUTPUT VOLTAGE pin (weak bleed). This

bleed current increases to ~200 mA (strong bleed) in the event that

the FEEDBACK pin voltage is raised beyond ~10% of the internal

FEEDBACK pin reference voltage. The current sink on the OUTPUT

VOLTAGE pin is intended to discharge the output voltage after

momentary overshoot events. The secondary does not relinquish

control to the primary during this mode of operation.

If the voltage on the FEEDBACK pin is sensed to be 20% higher than

the regulation threshold, a command is sent to the primary to either

latch-off or begin an auto-restart sequence (see Secondary Fault

Response in Feature Code Addendum). This integrated V

OUT OVP can

be used independently from the primary sensed OVP or in conjunction.

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