Sabre32 Reference Datasheet

February 11, 2010

CONFIDENTIAL ADVANCE

INFORMATION Rev. 1.2

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19

Vista™

High Definition

Vista™

High Definition

Registers #23-20: Master Trim

(default = 32’h7fffffff)

This is a 32 bit value that sets the 0dB level for all volume controls. This is a signed number, so it should

never exceed 32'h7fffffff (which is 2

31 - 1). (Reg 23 are the MSB’s, Reg 20 are the LSB’s)

Register 24: Phase Shift

(default = 8’b00110000)

[7:4]

RESERVED

[3:0]

phase_shift

4'd0 => default

4'd1 => default + 1/clk delay

4'd2 => default + 2/clk delay

4'd3 => default + 3/clk delay

4'd4 => default + 4/clk delay

4'd5 => default + 5/clk delay

4'd6 => default + 6/clk delay

4'd7 => default + 7/clk delay

4'd8 => default + 8/clk delay

4'd9 => default + 9/clk delay

4'd10 => default + 10/clk delay

4'd11 => default + 11/clk delay

4'd12 => default + 12/clk delay

4'd13 => default + 13/clk delay

4'd14 => default + 14/clk delay

4'd15 => default + 15/clk delay

Register 25: DPLL Mode Control

(default = 8’b00000010)

[7:2]

RESERVED

[1]

dpll_bw_defaults

1'b1 => Use the best DPLL bandwidth settings.

1'b0 => Allow all settings.

[0]

dpll_bw_128x

1'b1 => Multiply the DPLL BANDWIDTH setting by 128.

1'b0 => Use the DPLL BANDWIDTH setting.

Register 27: Status

This is a read-only register. All of these values are set by internal logic on the chip.

[7:4]

RESERVED

[3]

dsd_pcm

1'b1 => DSD mode.

1'b0 => I2S or SPDIF mode.

[2]

spdif_valid

1'b1 => The SPDIF data is valid.

1'b0 => The SPDIF data is invalid.

[1]

spdif_en

1'b1 => SPDIF mode is currently enabled. This can be done manually by setting

spdif_en_r (Register 8) or by having spdif_autodetect enabled with valid

SPDIF data on the input.

1'b0 => SPDIF mode is currently disabled.

[0]

lock

1'b1 => The Jitter Eliminator is locked to an incoming signal.

1'b0 => The Jitter Eliminator is not locked to an incoming signal.